Kerry S. Lowe

According to our database, Kerry S. Lowe authored at least 5 papers between 1993 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1998

A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic.

Kerry S. Lowe, P. Glenn Gulak

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

Bufferless broadcasting: a low power distributed circuit technique for broadcasting 10-Gb/s chip input signals.

Kerry S. Lowe

IEEE J. Solid State Circuits, 1997

A GaAs HBT 16×16 10-Gb/s/channel crosspoint switch.

Kerry S. Lowe

IEEE J. Solid State Circuits, 1997

1994

A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits.

Kerry S. Lowe, P. Glenn Gulak

Proceedings of the Proceedings EURO-DAC'94, 1994

1993

Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits.

Kerry S. Lowe, P. Glenn Gulak

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993