P. Glenn Gulak

According to our database1, P. Glenn Gulak authored at least 89 papers between 1986 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Hardware-Based Linear Program Decoding With the Alternating Direction Method of Multipliers.
IEEE Trans. Signal Process., 2019

2018
A Multi-Gb/s Frame-Interleaved LDPC Decoder With Path-Unrolled Message Passing in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Superresolution Line Scan Image Sensor for Multimodal Microscopy.
IEEE Trans. Biomed. Circuits Syst., 2018

A 70 pJ/b configurable 64-QAM soft MIMO detector.
Integr., 2018

2017
A 38 pJ/b Optimal Soft-MIMO Detector.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Key Reconciliation with Low-Density Parity-Check Codes for Long-Distance Quantum Cryptography.
CoRR, 2017

Hardware-based linear programming decoding via the alternating direction method of multipliers.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

2016
SHIELD: Scalable Homomorphic Implementation of Encrypted Data-Classifiers.
IEEE Trans. Computers, 2016

SecureMed: Secure Medical Computation using GPU-Accelerated Homomorphic Encryption Scheme.
IACR Cryptol. ePrint Arch., 2016

Hardware-Based ADMM-LP Decoding.
CoRR, 2016

2015
Design and Implementation of Time and Frequency Synchronization in LTE.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Fully Integrated On-Chip Coil in 0.13 µm CMOS for Wireless Power Transfer Through Biological Media.
IEEE Trans. Biomed. Circuits Syst., 2015

A CMOS sensor for rapid testing of pathogen susceptibility to pore-forming antibiotics.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

2013
Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

High-Throughput 0.13-µm CMOS Lattice Reduction Core Supporting 880 Mb/s Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

CMOS Tunable-Color Image Sensor With Dual-ADC Shot-Noise-Aware Dynamic Range Extension.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Rapid Detection of E. coli Bacteria Using Potassium-Sensitive FETs in CMOS.
IEEE Trans. Biomed. Circuits Syst., 2013

CMOS Tunable-Wavelength Multi-Color Photogate Sensor.
IEEE Trans. Biomed. Circuits Syst., 2013

CMOS Spectrally-Multiplexed FRET-on-a-Chip for DNA Analysis.
IEEE Trans. Biomed. Circuits Syst., 2013

2012
A 675 Mbps, 4 × 4 64-QAM K-Best MIMO Detector in 0.13 µm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Maximum Achievable Efficiency in Near-Field Coupled Power-Transfer Systems.
IEEE Trans. Biomed. Circuits Syst., 2012

Message From the Steering Committee.
IEEE Des. Test Comput., 2012

Fully-integrated, power-efficient regulator and bandgap circuits for wireless-powered biomedical applications.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

High-efficiency CMOS rectifier for fully integrated mW wireless power transfer.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Single-filter multi-color CMOS fluorescent contact sensing microsystem.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

CMOS 3-T digital pixel sensor with in-pixel shared comparator.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A robust RAM-THP architecture for downlink multiuser MISO transmission with user scheduling.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Performance analysis of lattice-reduction algorithms for a novel LR-compatible K-Best MIMO detector.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Downlink Beamforming for FDD Systems with Precoding and Beam Steering.
Proceedings of the Global Communications Conference, 2011

CMOS field-modulated color sensor.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A CMOS/Thin-Film Fluorescence Contact Imaging Microsystem for DNA Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

VLSI implementation of a hardware-optimized lattice reduction algorithm for WiMAX/LTE MIMO detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

VLSI implementation of a WiMAX/LTE compliant low-complexity high-throughput soft-output K-Best MIMO detector.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A 0.13µm CMOS 655Mb/s 4×4 64-QAM K-Best MIMO detector.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A Hybrid Thin-film/CMOS Fluorescence Contact Imager.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Low-complexity High-speed QR Decomposition Implementation for MIMO Receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Efficient Compensation of the Nonlinearity of Solid-State Power Amplifiers Using Adaptive Sequential Monte Carlo Methods.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A systolic architecture of a Sequential Monte Carlo-based equalizer for frequency-selective MIMO channels.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

A 0.18μm CMOS Integrated Sensor for the Rapid Identification of Bacteria.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Scalable VLSI architecture for K-best lattice decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

The application of lattice-reduction to the K-Best algorithm for near-optimal MIMO detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A pipelined scalable high-throughput implementation of a near-ML K-best complex lattice decoder.
Proceedings of the IEEE International Conference on Acoustics, 2008

2007
Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A Preprocessing Method for PAPR Reduction in OFDM Systems by Modifying FFT and IFFT Matrices.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

Application of Sequential Monte Carlo to M-QAM Schemes in the Presence of Nonlinear Solid-State Power Amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A CMOS Image Sensor for DNA Microarrays.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
An area-efficient universal cryptography processor for smart cards.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes.
IEEE Trans. Commun., 2006

An efficient architecture for distributed resampling for high-speed particle filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

VLSI implementation of a sequential Monte Carlo receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Papr Reduction in OFDM Systems Using Polynomial-Based Compressing and Iterative Expanding.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

2005
Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders.
J. VLSI Signal Process., 2005

On Multiple Slice Turbo Codes.
Ann. des Télécommunications, 2005

Iterative MIMO channel SVD estimation.
Proceedings of IEEE International Conference on Communications, 2005

2004
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
VLSI architectures for the MAP algorithm.
IEEE Trans. Commun., 2003

In-building power lines as high-speed communication channels: channel characterization and a test channel ensemble.
Int. J. Commun. Syst., 2003

2000
A discrete multitone power line communications system.
Proceedings of the IEEE International Conference on Acoustics, 2000

1999
Joint Data and Kalman Estimation for Rayleigh Fading Channels.
Wirel. Pers. Commun., 1999

1998
A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Parallel structures for joint channel estimation and data detection over fading channels.
IEEE J. Sel. Areas Commun., 1998

Implementation Issues for High-Bandwidth Field-Programmable Analog Arrays.
J. Circuits Syst. Comput., 1998

Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

A Review of Multiple-Valued Memory Technology.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1997
Physical performance limits for shared buffer ATM switches.
IEEE Trans. Commun., 1997

Authors' reply to "A note on architectures for large-capacity CAMs".
Integr., 1997

1996
Multicast contention resolution with single-cycle windowing using content addressable FIFO's.
IEEE/ACM Trans. Netw., 1996

A Multiple-Valued Ferroelectric Content-Addressable Memory.
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995
Architectures for large-capacity CAMs.
Integr., 1995

A Field-Programmable Mixed-Analog-Digital Array.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994
Reduced complexity symbol detectors with parallel structure for ISI channels.
IEEE Trans. Commun., 1994

Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.
Inf. Process. Manag., 1994

A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits.
Proceedings of the Proceedings EURO-DAC'94, 1994

Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression.
Proceedings of the IEEE Data Compression Conference, 1994

1993
A multiprocessor architecture for Viterbi decoders with linear speedup.
IEEE Trans. Signal Process., 1993

Architectural tradeoffs for survivor sequence memory management in Viterbi decoders.
IEEE Trans. Commun., 1993

A Logic-enhanced Memory for Digital Data Recovery Circuits.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding.
Proceedings of the IEEE Data Compression Conference, 1993

1992
Dynamic Current-Mode Multi-Valued MOS Memory with Error Correction.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991
Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up.
Proceedings of the 1991 International Conference on Acoustics, 1991

1988
Locally connected VLSI architectures for the Viterbi algorithm.
IEEE J. Sel. Areas Commun., 1988

1987
(lambda, <i>T</i>) Complexity Measures for VLSI Computations in Constant Chip Area.
IEEE Trans. Computers, 1987

1986
Dual Systolic Architectures for VLSI Digital Signal Processing Systems.
IEEE Trans. Computers, 1986

VLSI Structures for Viterbi Receivers: Part II-Encoded MSK Modulation.
IEEE J. Sel. Areas Commun., 1986

VLSI Structures for Viterbi Receivers: Part I-General Theory and Applications.
IEEE J. Sel. Areas Commun., 1986


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