Khosrov Dabbagh-Sadeghipour
According to our database1,
Khosrov Dabbagh-Sadeghipour
authored at least 9 papers
between 2003 and 2022.
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Bibliography
2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2015
Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2012
2011
Efficient realization of reconfigurable FIR filter using the new coefficient representation.
IEICE Electron. Express, 2011
A new hardware efficient reconfigurable fir filter architecture suitable for FPGA applications.
Proceedings of the 17th International Conference on Digital Signal Processing, 2011
2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
A new FPGA-based postprocessor architecture for channel mismatch correction of time interleaved ADCS.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
2008
A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003