Ki-Soo Lee

According to our database, Ki-Soo Lee authored at least 4 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of six.

2025

A V_M-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces.

Chanheum Han, Ki-Soo Lee, Jun-Cheol Lee, Joo-Hyung Chae

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025

25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter With Embedded Partial DBI: Improving I/O Bandwidth/pin and DBI Efficiencies.

Chanheum Han, Ki-Soo Lee, Joo-Hyung Chae

IEEE J. Solid State Circuits, May, 2025

A 0.9-V 15.6-Gb/s Single Ended NRZ Receiver with 1-Tap DFE for Low-Power Memory Interfaces.

Jongmin Lee, Ki-Soo Lee, Joo-Hyung Chae

Proceedings of the International Conference on Electronics, Information, and Communication, 2025

2024

13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency.

Chanheum Han, Ki-Soo Lee, Joo-Hyung Chae

Proceedings of the IEEE International Solid-State Circuits Conference, 2024