Kim B. Östman

Orcid: 0000-0001-7807-9271

According to our database1, Kim B. Östman authored at least 16 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Quantization noise upconversion effects in mixer-first direct delta-sigma receivers.
Int. J. Circuit Theory Appl., 2019

2018
A Systematic Design Method for Direct Delta-Sigma Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A common-gate common-source low noise amplifier based RF front end with selective input impedance matching for blocker-resilient receivers.
Int. J. Circuit Theory Appl., 2018

Analysis and Design of ESD Protection for Robust Low-Power Pierce Crystal Oscillator Startup.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Full-Duplex Wireless Transceiver Self-Interference Cancellation Through FD-SOI Buried-Gate Signaling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A wideband blocker-resilient direct ΔΣ receiver with selective input-impedance matching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A wideband blocker-resilient RF front-end with selective input-impedance matching for direct-ΔΣ-receiver architectures.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

2015
Analysis and Design of N-Path Filter Offset Tuning in a 0.7-2.7-GHz Receiver Front-End.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS.
IEEE J. Solid State Circuits, 2015

Next-Generation RF Front-End Design Methods for Direct ΔΣ Receivers.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

2014
A 3.6-to-1.8-V Cascode Buck Converter With a Stacked LC Filter in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Characteristics of LNA Operation in Direct Delta-Sigma Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator.
Proceedings of the ESSCIRC 2014, 2014

2013
Design tradeoffs in N-path GmC integrators for direct delta-sigma receivers.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2006
Novel VCO Architecture Using Series Above-IC FBAR and Parallel LC Resonance.
IEEE J. Solid State Circuits, 2006


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