Kari Stadius

According to our database1, Kari Stadius authored at least 58 papers between 1994 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
True-Time-Delay Beamforming Receiver With RF Re-Sampling.
IEEE Trans. Circuits Syst., 2020

Injection Locking of Ring Oscillators with Digitally Controlled Delay Modulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 3.5-GHz Digitally-Controlled Open-Loop Fractional-N Frequency Divider in 28-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 30-GHz Switched-Capacitor Power Amplifier for 5G SoCs.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Design of a 20-80 GHz Down-Conversion Mixer for 5G Wireless Communication with 22nm CMOS.
Proceedings of the 2nd 6G Wireless Summit, 2020

2019
A 1.5-1.9-GHz All-Digital Tri-Phasing Transmitter With an Integrated Multilevel Class-D Power Amplifier Achieving 100-MHz RF Bandwidth.
IEEE J. Solid State Circuits, 2019

Quantization noise upconversion effects in mixer-first direct delta-sigma receivers.
Int. J. Circuit Theory Appl., 2019

A Delay-Based LO Phase-Shifting Generator for a 2-5GHz Beamsteering Receiver in 28nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A Wideband IF Receiver Module for Flexibly Scalable mmWave Beamforming Combining and Interference Cancellation.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
A High-Speed DSP Engine for First-Order Hold Digital Phase Modulation in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Tri-Phasing Modulation for Efficient and Wideband Radio Transmitters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Systematic Design Method for Direct Delta-Sigma Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A common-gate common-source low noise amplifier based RF front end with selective input impedance matching for blocker-resilient receivers.
Int. J. Circuit Theory Appl., 2018

A 20-60GHz Digitally Controlled Composite Oscillator for 5G.
Proceedings of the 2018 New Generation of CAS, 2018

A 3-43ps time-delay cell for LO phase-shifting in 1.5-6.5GHz beamsteering receiver.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Spectral Effects of Discrete-Time Amplitude Levels in Digital-Intensive Wideband Radio Transmitters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Implementation of a Wideband Digital Interpolating Phase Modulator RF Front-End.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Full-Duplex Wireless Transceiver Self-Interference Cancellation Through FD-SOI Buried-Gate Signaling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
13.5 A 0.35-to-2.6GHz multilevel outphasing transmitter with a digital interpolating phase modulator enabling up to 400MHz instantaneous bandwidth.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A wideband blocker-resilient direct ΔΣ receiver with selective input-impedance matching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A charge limiting and redistribution method for delay line locking in multi-output clock generation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Open-loop all-digital delay line with on-chip calibration via self-equalizing delays.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016
Digital Interpolating Phase Modulator for Wideband Outphasing Transmitters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A wideband blocker-resilient RF front-end with selective input-impedance matching for direct-ΔΣ-receiver architectures.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Reference receiver enabled digital cancellation of nonlinear out-of-band blocker distortion in wideband receivers.
Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016

2015
Analysis and Design of N-Path Filter Offset Tuning in a 0.7-2.7-GHz Receiver Front-End.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS.
IEEE J. Solid State Circuits, 2015

Next-Generation RF Front-End Design Methods for Direct ΔΣ Receivers.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

A 0.8-3 GHz mixer-first receiver with on-chip transformer balun in 65-nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015

All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
RX-Band Noise Reduction in All-Digital Transmitters With Configurable Spectral Shaping of Quantization and Mismatch Errors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Characteristics of LNA Operation in Direct Delta-Sigma Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 1.2 - 6.4 GHz clock generator with a low-power DCO and programmable multiplier in 40-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator.
Proceedings of the ESSCIRC 2014, 2014

2013
A programmable DSP front-end for all-digital 4G transmitters.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A configurable sampling rate converter for all-digital 4G transmitters.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Design tradeoffs in N-path GmC integrators for direct delta-sigma receivers.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011
Electrical properties of CVD-graphene FETs.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

A 0.7 - 2.6 GHz high-linearity rf front-end for cognitive radio spectrum sensing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Implementation of all-digital wideband RF frequency synthesizers in 65-nm CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A 2.4-GHz Low-Power All-Digital Phase-Locked Loop.
IEEE J. Solid State Circuits, 2010

A wide-band digitally controlled ring oscillator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Spectral purity analysis of integer-N PLL.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A low-power wide-band digital frequency synthesizer for cognitive radio sensor units.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

Agile frequency synthesizer for cognitive radios.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
Analysis and Design of Passive Polyphase Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A WiMedia UWB receiver with a synthesizer.
Proceedings of the ESSCIRC 2008, 2008

2005
Development of 4-GHz flip-chip VCO module.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Characteristics and modeling of a broadband transmission-line transformer.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A broadband upconverter unit for double-conversion receivers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
Monolithic tunable capacitors for RF applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Image-reject receivers with image-selection functionality.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A novel BJT output stage for SAW drivers.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1999
Design of a fully integrated 2 GHz CMOS frequency synthesizer.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1994
Q-Enhancing Technique for High Speed Active Inductors.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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