Kishore Pula

According to our database1, Kishore Pula authored at least 4 papers in 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Reverse Engineering of RTL Controllers from Look-Up Table Netlists.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Reverse Engineering Word-Level Models from Look-Up Table Netlists.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023


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