Aparajithan Nathamuni Venkatesan

According to our database, Aparajithan Nathamuni Venkatesan authored at least 5 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Reverse Engineering RTL Models from DSP Slices in FPGA Netlists.

Avinash Hegde Kota, Aparajithan Nathamuni Venkatesan, Ranga Vemuri, John Marty Emmert

Proceedings of the 27th International Symposium on Quality Electronic Design, 2026

2023

Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information.

Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks.

Kishore Pula, Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Sundarakumar Muthukumaran, Ranga Vemuri, John Marty Emmert

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Reverse Engineering of RTL Controllers from Look-Up Table Netlists.

Sundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri, John Marty Emmert

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Reverse Engineering Word-Level Models from Look-Up Table Netlists.

Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023