Kiyotaka Komoku

According to our database1, Kiyotaka Komoku authored at least 16 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Study of 18.2-42.0GHz injection-locked frequency doubler with transformer input.
IEICE Electron. Express, 2023

2022
920MHz current-reuse low-power LNA operated in moderate inversion region.
IEICE Electron. Express, 2022

28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

2021
Study of dual-band concurrent LNA equipping mutual inductive notch filter matching circuit.
IEICE Electron. Express, 2021

2018
Modeling and Layout Optimization of MOM Capacitor for High-Frequency Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Interpolation Based Unbounded Model Checking for Time Petri Nets.
Proceedings of the IEEE 7th Global Conference on Consumer Electronics, 2018

2016
A Study of Striped Inductor for K- and Ka-Band Voltage-Controlled Oscillators.
IEICE Trans. Electron., 2016

A study of current-reuse 800 MHz/1.9 GHz concurrent dual-band amplifier.
Proceedings of the 2016 IEEE Radio and Wireless Symposium, 2016

3D<sup>2</sup> processing architecture - High reliability and low power computing for novel nano tactile sensor array.
Proceedings of the International SoC Design Conference, 2016

2009
Current-Voltage Hysteresis Characteristics in MOS Capacitors with Si-Implanted Oxide.
IEICE Trans. Electron., 2009

2008
A Test Structure for Asymmetry and Orientation Dependence Analysis of CMOSFETs.
IEICE Trans. Electron., 2008

2007
A CMOS Temperature Sensor Circuit.
IEICE Trans. Electron., 2007

A Test Structure to Analyze Electrical CMOSFET Reliabilities between Center and Edge along the Channel Width.
IEICE Trans. Electron., 2007

2006
A Test Structure to Analyze Highly-Doped-Drain and Lightly-Doped-Drain in CMOSFET.
IEICE Trans. Electron., 2006

1999
Implementation of cell array neuro-processor by using FPGA.
Proceedings of the International Joint Conference Neural Networks, 1999

Development support software of cell array processor and its neural network application.
Proceedings of the International Joint Conference Neural Networks, 1999


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