Kazutami Arimoto

According to our database, Kazutami Arimoto authored at least 84 papers between 1985 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Applying Symbolic Model Checking to Node-graph Style Game Scripts with Time Constraints.

Ryugo Tanaka, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2022

28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System.

Yuji Yano, Hisashi Iwamoto, Takuma Yoshimura, Yoshihiro Nishida, Tatsuya Mori, Kiyotaka Komoku, Hidekuni Takao, Kazutami Arimoto

Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

Verifying Game Logic in Unreal Engine 5 Blueprint Visual Scripting System Using Model Checking.

Kazuki Wayama, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto

Proceedings of the 37th IEEE/ACM International Conference on Automated Software Engineering, 2022

A Visual Modeling Environment for the nuXmv Model Checker Intended for Novice Users.

Kazuma Toyota, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto

Proceedings of the 12th International Congress on Advanced Applied Informatics, 2022

2021

Localized Data Transfer System by Vehicles and Cellular Base Station in Local Area.

Hiroshi Miyata, Kazutami Arimoto

Proceedings of the IEEE International Conference on Communications Workshops, 2021

New Value Creation by Nano-Tactile Sensor Chip Exceeding our Fingertip Discrimination Ability.

Hidekuni Takao, Kazuki Watatani, Kazutami Arimoto

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020

Symbolic Representation of Time Petri Nets for Efficient Bounded Model Checking.

Nao Igawa, Tomoyuki Yokogawa, Sousuke Amasaki, Masafumi Kondo, Yoichiro Sato, Kazutami Arimoto

IEICE Trans. Inf. Syst., 2020

A Edge Master Computing for Pineapple Monitoring System with Drone and Data-management.

Tomoki Kobayashi, Tomoyuki Yokogawa, Nao Igawa, Yoichiro Sato, Kimihoro Sugino, Hiroshi Miyata, Satoshi Fujii, Kazutami Arimoto

Proceedings of the 9th International Congress on Advanced Applied Informatics, 2020

Model Checking of Visual Scripts Created by UE4 Blueprints.

Nao Igawa, Tomoyuki Yokogawa, Mami Takahashi, Kazutami Arimoto

Proceedings of the 9th International Congress on Advanced Applied Informatics, 2020

A Node-Style Visual Programming Environment for the nuXmv Model Checker.

Hayato Naito, Tomoyuki Yokogawa, Nao Igawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto

Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

2019

Consistency Verification of UML Sequence Diagrams Modeling Wireless Sensor Networks.

Akira Matsumoto, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto

Proceedings of the 8th International Congress on Advanced Applied Informatics, 2019

A Compact Low Power AI Module Mounted on Drone for Plant Monitor System.

Tomoki Kobayashi, Tomoyuki Yokogawa, Nao Igawa, Yoichiro Sato, Satoshi Fujii, Kazutami Arimoto

Proceedings of the 8th International Congress on Advanced Applied Informatics, 2019

Radio link design for ITS integrated network using drone.

Satoshi Fujii, Issei Nakaema, Kei Miyagi, Shouichiro Tanifuji, Noriaki Yoshikawa, Kensaku Kinoshita, Kazutami Arimoto

Proceedings of the IEEE VTS Asia Pacific Wireless Communications Symposium, 2019

2018

Interpolation Based Unbounded Model Checking for Time Petri Nets.

Nao Igawa, Tomoyuki Yokogawa, Sousuke Amasaki, Kiyotaka Komoku, Yoichiro Sato, Kazutami Arimoto

Proceedings of the IEEE 7th Global Conference on Consumer Electronics, 2018

2017

Tool Support for Consistency Verification of UML Diagrams.

Salilthip Phuklang, Tomoyuki Yokogawa, Pattara Leelaprute, Kazutami Arimoto

Proceedings of the Product-Focused Software Process Improvement, 2017

A smart low power R-R-I heartbeat monitor system with contactless UWB sensor.

Kazutami Arimoto, Daichi Yamashita, Nao Igawa, Tomoyuki Yokogawa, Yoichiro Sato, Isao Kayano, Akio Shiratori

Proceedings of the International SoC Design Conference, 2017

2016

A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals.

Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

3D² processing architecture - High reliability and low power computing for novel nano tactile sensor array.

Kiyotaka Komoku, Kazutami Arimoto, Tomoyuki Yokogawa, Hitoshi Yamauchi, Yoichiro Sato, Hidekuni Takao

Proceedings of the International SoC Design Conference, 2016

A Serial Booth Multiplier Using Ring Oscillator.

Daichi Okamoto, Masafumi Kondo, Tomoyuki Yokogawa, Yoshihiro Sejima, Kazutami Arimoto, Yoichiro Sato

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015

Bounded model checking of Time Petri Nets using SAT solver.

Tomoyuki Yokogawa, Masafumi Kondo, Hisashi Miyazaki, Sousuke Amasaki, Yoichiro Sato, Kazutami Arimoto

IEICE Electron. Express, 2015

2014

F5: Low-power radios for sensor networks.

Woogeun Rhee, Gangadhar Burra, Kazutami Arimoto, Pieter Harpe, Brian Otis, David Ruffieux

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

The LSI implementation of a memory based field programmable device for MCU peripherals.

Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013

Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System.

Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto

IEEE J. Solid State Circuits, 2013

Consistency Verification of UML Diagrams Based on Process Bisimulation.

Tomoyuki Yokogawa, Sousuke Amasaki, Keisuke Okazaki, Yoichiro Sato, Kazutami Arimoto, Hisashi Miyazaki

Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

2012

What's next in robots? ∼Sensing, processing, networking toward human brain and body.

Kazutami Arimoto, Sam Kavusi, Kenneth Salisbury

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A Scalable Massively Parallel Processor for Real-Time Image Processing.

Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto

IEEE J. Solid State Circuits, 2011

Low Power Platform for Embedded Processor LSIs.

Toru Shimizu, Kazutami Arimoto, Osamu Nishii, Sugako Otani, Hiroyuki Kondo

IEICE Trans. Electron., 2011

An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs.

Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

PEARL and PEACH: A Novel PCI Express Direct Link and Its Implementation.

Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, Kazutami Arimoto

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G.

Yushi Moko, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa, Masami Nakajima, Kazutami Arimoto

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2011

An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller.

Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato

Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

2010

Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation.

Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Fusion of MEMS and circuits.

Satoshi Shigematsu, Kazutami Arimoto, Christoph Hagleitner

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A scalable massively parallel processor for real-time image processing.

Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

PEARL: Power-Aware, Dependable, and High-Performance Communication Link Using PCI Express.

Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, Kazutami Arimoto

Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications, 2010

2009

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications.

Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu

IEEE J. Solid State Circuits, 2009

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform.

Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto

IEICE Trans. Electron., 2009

A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test.

Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto

IEICE Trans. Electron., 2009

2008

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors.

Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto

IEEE J. Solid State Circuits, 2008

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor.

Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito

IEICE Trans. Electron., 2008

Heterogeneous multicore SoC for secure multimedia applications.

Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture.

Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto

IEEE J. Solid State Circuits, 2007

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.

Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu

IEEE J. Solid State Circuits, 2007

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory.

Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto

IEEE J. Solid State Circuits, 2007

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs.

Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi

IEEE J. Solid State Circuits, 2007

A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform.

Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto

IEICE Trans. Electron., 2007

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI.

Fukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto

IEICE Trans. Electron., 2007

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer.

Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito

IEICE Trans. Inf. Syst., 2007

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor.

Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito

IEICE Trans. Inf. Syst., 2007

Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS.

Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu

IEICE Trans. Electron., 2007

A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test.

Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.

Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine.

Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC.

Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto

IEICE Trans. Electron., 2006

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design.

Takayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba

IEICE Trans. Electron., 2006

A 40GOPS 250mW massively parallel processor based on matrix architecture.

Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI.

Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture.

Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2005

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications.

Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2005

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning.

Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto

IEEE J. Solid State Circuits, 2005

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros.

Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara

IEICE Trans. Electron., 2005

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh.

Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

IEICE Trans. Electron., 2005

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features.

Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide

IEICE Trans. Electron., 2005

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example].

Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM.

Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A capacitorless twin-transistor random access memory (TTRAM) on SOI.

Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write.

Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto

IEEE J. Solid State Circuits, 2003

A Low Power Embedded DRAM Macro for Battery-Operated LSIs.

Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2001

Design methodology of embedded DRAM with virtual-socket architecture.

Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2001

Test cost reduction by at-speed BISR for embedded DRAMs.

Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

High-performance embedded SOI DRAM architecture for the low-power supply.

Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

1999

A 5.3-GB/s embedded SDRAM core with slight-boost scheme.

Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada

IEEE J. Solid State Circuits, 1999

1998

400-MHz random column operating SDRAM techniques with self-skew compensation.

Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada

IEEE J. Solid State Circuits, 1998

1997

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's.

Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada

IEEE J. Solid State Circuits, 1997

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme.

Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto

IEEE J. Solid State Circuits, 1997

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique.

Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma

IEEE J. Solid State Circuits, 1997

1996

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.

Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe

IEEE J. Solid State Circuits, 1996

SOI-DRAM circuit technologies for low power high speed multigiga scale memories.

Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto

IEEE J. Solid State Circuits, 1996

1995

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs.

Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto

IEEE J. Solid State Circuits, November, 1995

1994

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.

Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima

IEEE J. Solid State Circuits, April, 1994

1993

Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters.

Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima

IEEE Des. Test Comput., 1993

1992

A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter.

Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1989

A New Array Architecture for Parallel Testing in VLSI Memories.

Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima

Proceedings of the Proceedings International Test Conference 1989, 1989

1985

Test Pattern Considerations for Fault Tolerant High Density DRAM.

Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano

Proceedings of the Proceedings International Test Conference 1985, 1985