Jun Furuta
According to our database1,
Jun Furuta
authored at least 26 papers
between 2010 and 2023.
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Bibliography
2023
Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation.
Proceedings of the International Conference on IC Design and Technology, 2023
Proceedings of the International Conference on IC Design and Technology, 2023
2022
Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
2021
An E-mode p-GaN HEMT monolithically-integrated three-level gate driver operating with a single voltage supply.
IEICE Electron. Express, 2021
2020
Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters.
IEICE Trans. Electron., 2020
2019
Integr., 2019
Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process.
IEICE Electron. Express, 2019
An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process.
IEICE Trans. Electron., 2018
Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
2015
Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets.
IEICE Trans. Electron., 2015
2013
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect.
IEICE Trans. Electron., 2013
2011
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEICE Trans. Electron., 2010