Kouji Matsuda

According to our database, Kouji Matsuda authored at least 3 papers between 1991 and 1994.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1994

A 200 MHz 13 mm² 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme.

Masataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai

IEEE J. Solid State Circuits, December, 1994

1992

0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file.

Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba

IEEE J. Solid State Circuits, November, 1992

1991

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network.

Kenji Sakaue, Yasuro Shobatake, Masahiko Motoyama, Yoshinari Kumaki, Satoru Takatsuka, Shigeru Tanaka, Hiroyuki Hara, Kouji Matsuda, Shuji Kitaoka, Makoto Noda, Youichiro Niitsu, Masayuki Norishima, Hiroshi Momose, Kenji Maeguchi, Manabu Ishibe, Shoichi Shimizu, Toshikazu Kodama

IEEE J. Solid State Circuits, August, 1991