Kwangmin Lim

According to our database, Kwangmin Lim authored at least 4 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm.

Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee

IEEE J. Solid State Circuits, December, 2024

9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm.

Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee, Sung-Ung Kwak

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module.

Joomyoung Kim, Jaehong Jung, Kwangmin Lim, Barosaim Sung, Jaekwon Kim, Baekmin Lim, Tae-Gun Noh, Jaehoon Lee, Hyun-Gi Seok, Youngsea Cho, Gyusik Kim, Takahiro Nomiyama, Sunhye Kang, Yeongcheol Jeong, Sanguk Cho, Gyumin Kim, Do-Hyun Oh, Jaenam Kim, Yong Lim, Seungjin Kim, Seunghyun Oh, Jongwoo Lee

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2021

Vertical and lateral charge losses during short time retention in 3-D NAND flash memory.

Yongwoo Lee, Jinsu Yoon, Kwangmin Lim, Bongsik Choi, Geon-Hwi Park, Ju Won Jeon, Jong-Ho Bae, Dong Myong Kim, Dae Hwan Kim, Eunmee Kwon, Sung-Jin Choi

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021