Kyoung Youn Cho

According to our database, Kyoung Youn Cho authored at least 4 papers between 2005 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

A scan cell architecture for inter-clock at-speed delay testing.

Kyoung Youn Cho, Rajagopalan Srinivasan

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2007

Test Set Reordering Using the Gate Exhaustive Test Metric.

Kyoung Youn Cho, Edward J. McCluskey

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

California scan architecture for high quality and low power testing.

Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey

Proceedings of the 2007 IEEE International Test Conference, 2007

2005

Gate exhaustive testing.

Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005