Subhasish Mitra

According to our database1, Subhasish Mitra authored at least 227 papers between 1997 and 2020.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2014, "For contributions to the design and testing of robust computing systems.".

IEEE Fellow

IEEE Fellow 2013, "For contributions to design and test of robust integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Scanning the Issue.
Proc. IEEE, 2020

A Density Metric for Semiconductor Technology [Point of View].
Proc. IEEE, 2020

Message from the Technical Program Co-Chairs.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Sensory Particles with Optical Telemetry.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Theoretical Framework for Symbolic Quick Error Detection.
Proceedings of the 2020 Formal Methods in Computer Aided Design, 2020

Gap-free Processor Verification by S<sup>2</sup>QED and Property Generation.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A-QED Verification of Hardware Accelerators.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording.
IEEE Trans. Biomed. Circuits Syst., 2019

The N3XT Approach to Energy-Efficient Abundant-Data Computing.
Proc. IEEE, 2019

Monolithic 3-D Integration.
IEEE Micro, 2019

Variability Expeditions: A Retrospective.
IEEE Des. Test, 2019

Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Optimization of Electrical Stimulation for a High-Fidelity Artificial Retina.
Proceedings of the 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019

A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration.
IEEE J. Solid State Circuits, 2018

Hyperdimensional Computing Nanosystem.
CoRR, 2018

Abundant-data computing: The N3XT 1, 000X.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Coming Up N3XT, After 2D Scaling of Si CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Symbolic quick error detection using symbolic initial state for pre-silicon verification.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Resistive RAM-Centric Computing: Design and Modeling Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

System-Level Effects of Soft Errors in Uncore Components.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Hot Chips 28.
IEEE Micro, 2017

Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2017

Edward J. McCluskey 1929-2016.
IEEE Des. Test, 2017

Logic Bug Detection and Localization Using Symbolic Quick Error Detection.
CoRR, 2017

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017


A Systems Approach to Computing in Beyond CMOS Fabrics: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

3D nanosystems enable <i>embedded</i> abundant-data computing: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods.
Proceedings of the Computer Aided Verification - 29th International Conference, 2017

ASP-DAC 2017 keynote speech I: In memory of Edward J. McCluskey: The next wave of pioneering innovations.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions.
IEEE Des. Test, 2016

Transforming nanodevices to next generation nanosystems.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Transforming nanodevices into nanosystems: The N3XT 1, 000X.
Proceedings of the 17th Latin-American Test Symposium, 2016

Session 24 overview: Ultra-efficient computing: Application-inspired and analog-assisted digital.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Cross-layer resilience.
Proceedings of the 21th IEEE European Test Symposium, 2016

Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Nano-engineered architectures for ultra-low power wireless body sensor nodes.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

New Logic Synthesis as Nanotechnology Enabler.
Proc. IEEE, 2015

NSF expedition on variability-aware software: Recent results and contributions.
it Inf. Technol., 2015

Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x.
Computer, 2015

A structured approach to post-silicon validation and debug using symbolic quick error detection.
Proceedings of the 2015 IEEE International Test Conference, 2015

Time-based sensor interface circuits in carbon nanotube technology.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Monolithic 3D integration: a path from concept to reality.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Efficient soft error vulnerability estimation of complex designs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Quick error detection tests with fast runtimes for effective post-silicon validation and debug.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Understanding soft errors in uncore components.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Multiple Independent Gate FETs: How many gates do we need?
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs.
IEEE J. Solid State Circuits, 2014

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2014

Addressing failures in exascale computing.
Int. J. High Perform. Comput. Appl., 2014

Guest Editorial: Robust and energy-secure systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

The resilience wall: Cross-layer solution strategies.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Welcome message.
Proceedings of the 2014 International Test Conference, 2014

A new era of computing: Are you "ready now" to build a smarter and secured enterprise?
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Carbon nanotube computer: transforming scientific discoveries into working systems.
Proceedings of the International Symposium on Physical Design, 2014

QED post-silicon validation and debug: Invited abstract.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Cross layer resiliency in real world.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Robust design and experimental demonstrations of carbon nanotube digital circuits.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Rethinking error injection for effective resilience.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

QED post-silicon validation and debug: Frequently asked questions.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Underdesigned and Opportunistic Computing in Presence of Hardware Variability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Combinational Logic Design Using Six-Terminal NEM Relays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Early-life-failure detection using SAT-based ATPG.
Proceedings of the 2013 IEEE International Test Conference, 2013

Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study.
Proceedings of the 2013 IEEE International Test Conference, 2013

Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Carbon nanotube imperfection-immune digital VLSI.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Carbon nanotube circuits: opportunities and challenges.
Proceedings of the Design, Automation and Test in Europe, 2013

Overcoming post-silicon validation challenges through quick error detection (QED).
Proceedings of the Design, Automation and Test in Europe, 2013

Sacha: the Stanford carbon nanotube controlled handshaking robot.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Quantitative evaluation of soft error injection techniques for robust system design.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Carbon Nanotube Robust Digital VLSI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

ERSA: Error Resilient System Architecture for Probabilistic Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Editorial.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing.
Proceedings of the 25th International Conference on VLSI Design, 2012

Probabilistic analysis of Gallager B faulty decoder.
Proceedings of IEEE International Conference on Communications, 2012

Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Quick detection of difficult bugs for effective post-silicon validation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Bug localization techniques for effective post-silicon validation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Robust System Design.
IPSJ Trans. Syst. LSI Des. Methodol., 2011

Robust System Design to Overcome CMOS Reliability Challenges.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

The case for RAMCloud.
Commun. ACM, 2011

Architecture and performance evaluation of 3D CMOS-NEM FPGA.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Post-silicon bug localization for processors using IFRA.
Commun. ACM, 2010

Concurrent autonomous self-test for uncore components in system-on-chips.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Gate-oxide early-life failure identification using delay shifts.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Robust System Design.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

QED: Quick Error Detection tests for effective post-silicon validation.
Proceedings of the 2011 IEEE International Test Conference, 2010

Cross-layer error resilience for robust systems.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Efficient FPGAs using nanoelectromechanical relays.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Carbon nanotube circuits: Living with imperfections and variations.
Proceedings of the Design, Automation and Test in Europe, 2010

Cross-layer resilience challenges: Metrics and optimization.
Proceedings of the Design, Automation and Test in Europe, 2010

Optimized self-tuning for circuit aging.
Proceedings of the Design, Automation and Test in Europe, 2010

ERSA: Error Resilient System Architecture for probabilistic applications.
Proceedings of the Design, Automation and Test in Europe, 2010

Statistical static timing analysis using Markov chain Monte Carlo.
Proceedings of the Design, Automation and Test in Europe, 2010

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.
Proceedings of the 47th Design Automation Conference, 2010

BLoG: post-silicon bug localization in processors using bug localization graphs.
Proceedings of the 47th Design Automation Conference, 2010

Post-silicon validation opportunities, challenges and recent advances.
Proceedings of the 47th Design Automation Conference, 2010

2009
Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

The case for RAMClouds: scalable high-performance storage entirely in DRAM.
ACM SIGOPS Oper. Syst. Rev., 2009

Overcoming Early-Life Failure and Aging for Robust Systems.
IEEE Des. Test Comput., 2009

Testing for Transistor Aging.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Imperfection-immune Carbon Nanotube digital VLSI.
Proceedings of the 27th International Conference on Computer Design, 2009

Operating system scheduling for efficient online self-test in robust systems.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

IFRA: Post-silicon bug localization in processors.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors.
Proceedings of the Design, Automation and Test in Europe, 2009

Carbon nanotube circuits in the presence of carbon nanotube density variations.
Proceedings of the 46th Design Automation Conference, 2009

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.
Proceedings of the 46th Design Automation Conference, 2009

Circuit aging prediction for low-power operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

The Search for Alternative Computational Paradigms.
IEEE Des. Test Comput., 2008

Historical Perspective on Scan Compression.
IEEE Des. Test Comput., 2008

Gate-Oxide Early Life Failure Prediction.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

VAST: Virtualization-Assisted Concurrent Autonomous Self-Test.
Proceedings of the 2008 IEEE International Test Conference, 2008

Optimized Circuit Failure Prediction for Aging: Practicality and Promise.
Proceedings of the 2008 IEEE International Test Conference, 2008

Tutorial 4: Robust System Design in Scaled CMOS.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Soft Error Protection Techniques.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Reliable system design: models, metrics and design techniques.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges.
Proceedings of the Design, Automation and Test in Europe, 2008

CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns.
Proceedings of the Design, Automation and Test in Europe, 2008

Soft Errors: System Effects, Protection Techniques and Case Studies.
Proceedings of the Design, Automation and Test in Europe, 2008

IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors.
Proceedings of the 45th Design Automation Conference, 2008

2007
Application-Dependent Delay Testing of FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Circuit Failure Prediction and Its Application to Transistor Aging.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Circuit failure prediction to overcome scaled CMOS reliability challenges.
Proceedings of the 2007 IEEE International Test Conference, 2007

California scan architecture for high quality and low power testing.
Proceedings of the 2007 IEEE International Test Conference, 2007

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Soft Errors: Technology Trends, System Effects, and Protection Techniques.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Verification-guided soft error resilience.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.
Proceedings of the 44th Design Automation Conference, 2007

2006
Sequential Element Design With Built-In Soft Error Resilience.
IEEE Trans. Very Large Scale Integr. Syst., 2006

XPAND: An Efficient Test Stimulus Compression Technique.
IEEE Trans. Computers, 2006

Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Soft Error Resilient System Design through Error Correction.
Proceedings of the IFIP VLSI-SoC 2006, 2006

How To Safeguard Your Sensitive Data.
Proceedings of the 25th IEEE Symposium on Reliable Distributed Systems (SRDS 2006), 2006

Test Compression for FPGAs.
Proceedings of the 2006 IEEE International Test Conference, 2006

Signature Analyzer Design for Yield Learning Support.
Proceedings of the 2006 IEEE International Test Conference, 2006

Combinational Logic Soft Error Correction.
Proceedings of the 2006 IEEE International Test Conference, 2006

Should Logic SER be Solved at the Circuit Level?
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2005
Application-independent testing of FPGA interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Optimized reseeding by seed ordering and encoding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Recent Advances and New Avenues in Hardware-Level Reliability Support.
IEEE Micro, 2005

X-Tolerant Test Response Compaction.
IEEE Des. Test Comput., 2005

Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim.
Computer, 2005

Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Enabling yield analysis with X-compact.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Logic soft errors: a major barrier to robust platform design.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Gate exhaustive testing.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

DFT Assisted Built-In Soft Error Resilience.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Response compaction with any number of unknowns using a new LFSR architecture.
Proceedings of the 42nd Design Automation Conference, 2005

Logic soft errors in sub-65nm technologies design and CAD challenges.
Proceedings of the 42nd Design Automation Conference, 2005

Robust platform design in advanced VLSI technologies.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Techniques and algorithms for fault grading of FPGA interconnect test configurations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

X-compact: an efficient response compaction technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Efficient Design Diversity Estimation for Combinational Circuits.
IEEE Trans. Computers, 2004

Reconfigurable Architecture for Autonomous Self-Repair.
IEEE Des. Test Comput., 2004

Conference Reports.
IEEE Des. Test Comput., 2004

Delay Defect Screening using Process Monitor Structures.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

ELF-Murphy Data on Defects and Test Sets.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Interconnect Delay Testing of Designs on Programmable Logic Devices.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

X-Tolerant Signature Analysis.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Speed Clustering of Integrated Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Defect and Fault Tolerance of Reconfigurable Molecular Computing.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
Delay Defect Characteristics and Testing Strategies.
IEEE Des. Test Comput., 2003

Efficient Seed Utilization for Reseeding based Compression.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Automatic Configuration Generation for FPGA Interconnect Testing.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Bist Reseeding with very few Seeds.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

XMAX: X-Tolerant Architecture for MAXimal Test Compression.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
ED4I: Error Detection by Diverse Data and Duplicated Instructions.
IEEE Trans. Computers, 2002

A Design Diversity Metric and Analysis of Redundant Systems.
IEEE Trans. Computers, 2002

Design for Testability and Testing of IEEE 1149.1 Tap Controller.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Debating the Future of Burn-In.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Test Vector Compression Using EDA-ATE Synergies.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Packet-Based Input Test Data Compression Techniques.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Fault Grading FPGA Interconnect Test Configurations.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Dependable Reconfigurable Computing Design Diversity and Self Repair.
Proceedings of the 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 2002

Testing Digital Circuits with Constraints.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
An Evaluation of Pseudo Random Testing for Detecting Real Defects.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Design of Redundant Systems Protected Against Common-Mode Failures.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Design Diversity for Concurrent Error Detection in Sequential Logic Circuts.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Diversity Techniques for Concurrent Error Detection.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Techniques for Estimation of Design Diversity for Combinational Logic Circuits.
Proceedings of the 2001 International Conference on Dependable Systems and Networks (DSN 2001) (formerly: FTCS), 2001

Fast Run-Time Fault Location in Dependable FPGA-Based Applications.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Common-mode failures in redundant VLSI systems: a survey.
IEEE Trans. Reliab., 2000

Dependable Computing and Online Testing in Adaptive and Configurable Systems.
IEEE Des. Test Comput., 2000

Efficient Multiplexer Synthesis Techniques.
IEEE Des. Test Comput., 2000

Fault Escapes in Duplex Systems.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Word Voter: A New Voter Design for Triple Modular Redundant Systems.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Which concurrent error detection scheme to choose ?
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Combinational logic synthesis for diversity in duplex systems.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
An output encoding problem and a solution technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A design diversity metric and reliability analysis for redundant systems.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1997
Scan Synthesis for One-Hot Signals.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997


  Loading...