Kyung-Sub Son
Orcid: 0000-0002-1013-1675Affiliations:
- Inha University, Incheon, South Korea
According to our database1,
Kyung-Sub Son
authored at least 15 papers
between 2014 and 2020.
Collaborative distances:
Collaborative distances:
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Bibliography
2020
A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
2019
A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEICE Electron. Express, 2019
IEICE Electron. Express, 2019
2018
Proceedings of the International SoC Design Conference, 2018
2017
A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector.
IEICE Electron. Express, 2017
2016
IEICE Electron. Express, 2016
A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector.
Proceedings of the International SoC Design Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR.
IEICE Electron. Express, 2015
IEICE Electron. Express, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS.
IEICE Electron. Express, 2014
A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection.
IEICE Electron. Express, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014