Jin-Ku Kang

Proceedings of the 20th International SoC Design Conference, 2023

A PAM-4 Baud-Rate CDR with High-Gain Phase Detector Using Shared Sampler.

[BibT_eX]

[DOI]

Seoung-Geun Cho

Proceedings of the 20th International SoC Design Conference, 2023

An FPGA-based Lightweight Deblocking CNN for Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

A Low-Cost Fully Integer-Based CNN Accelerator on FPGA for Real-Time Traffic Sign Recognition.

[BibT_eX]

[DOI]

IEEE Access, 2022

Target Capacity Filter Pruning Method for Optimized Inference Time Based on YOLOv5 in Embedded Systems.

[BibT_eX]

[DOI]

IEEE Access, 2022

An Overhead-Reduced Key Coding Technique for High-Speed Serial Interface.

[BibT_eX]

[DOI]

IEEE Access, 2022

A Design and Implementation of MIPI A-PHY RTS Layer.

[BibT_eX]

[DOI]

Sang-Ung Shin

Proceedings of the 19th International SoC Design Conference, 2022

An FPGA Implementation of CNN-based Compression Artifact Reduction.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

High-speed Serial Interface using PWAM Signaling Scheme.

[BibT_eX]

[DOI]

Hwan-Ung Kim

Proceedings of the 19th International SoC Design Conference, 2022

A Wide-range Low Power Quarter Rate Single Loop CDR.

[BibT_eX]

[DOI]

Jin-Ho Kim

Proceedings of the 19th International SoC Design Conference, 2022

A Low-Power Counter-based Digital CDR.

[BibT_eX]

[DOI]

Hyun-In Kim

Proceedings of the 19th International SoC Design Conference, 2022

Filter Pruning Method for Inference Time Acceleration Based on YOLOX in Edge Device.

[BibT_eX]

[DOI]

Jihun Jeon

Proceedings of the 19th International SoC Design Conference, 2022

2021

A 0.32-2.7 Gb/s Reference-Less Continuous-Rate Clock and Data Recovery Circuit With Unrestricted and Fast Frequency Acquisition.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Resource Efficient Integer-Arithmetic-Only FPGA-Based CNN Accelerator for Real-Time Facial Emotion Recognition.

[BibT_eX]

[DOI]

IEEE Access, 2021

Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuit.

[BibT_eX]

[DOI]

Chang han Rho

Jin Liu

Proceedings of the 18th International SoC Design Conference, 2021

An 8 - 26 Gb/s Single Loop Reference-less CDR with Unrestricted Frequency Acquisition.

[BibT_eX]

[DOI]

Hyung-Wook Lee

Kyeong-Min Ko

Proceedings of the 18th International SoC Design Conference, 2021

Design of 20Gb/s PAM4 Transmitter with Maximum Transition Elimination and Transition Compensation Techniques.

[BibT_eX]

[DOI]

Kyeong-Min Ko

Dohyeon Kwon

Proceedings of the 18th International SoC Design Conference, 2021

2020

A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019

A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Eye-open monitor using two-dimensional counter value profile.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

Design of a third-order delta-sigma TDC with error-feedback structure.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

2018

A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

2017

A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector.

[BibT_eX]

[DOI]

Nguyen Huu Tho

IEICE Electron. Express, 2017

2016

A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's.

[BibT_eX]

[DOI]

Bum-Hee Choi

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

A Link Layer Design for DisplayPort Interface with State Machine Based Packet Processing.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2015

On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

Precise time-difference repetition for TDC with delay mismatch cancelling scheme.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

On-chip jitter tolerance measurement technique for CDR circuits.

[BibT_eX]

[DOI]

Kyongsu Lee

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

A 2.2-mW 20-135-MHz False-Lock-Free DLL for Display Interface in 0.15-µm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Automatic SfM-Based 2D-to-3D Conversion for Multi-Object Scenes.

[BibT_eX]

[DOI]

Hak Gu Kim

Byung Cheol Song

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

A low jitter clock and data recovery with a single edge sensing Bang-Bang PD.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Avoiding noise frequency interference with binary phase pulse driving and CDS for capacitive TSP controller.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

An ultra-low power BPSK demodulator with dual band filtering for implantable biomedical devices.

[BibT_eX]

[DOI]

Joon-Hyup Seo

Jin-Cheol Seo

IEICE Electron. Express, 2013

A low power BPSK demodulator for wireless implantable biomedical devices.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Three-dimensional perception improvement using sharpness adjustment and hardware implementation.

[BibT_eX]

[DOI]

Hak Gu Kim

Byung Cheol Song

Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, 2013

2012

Video denoising using overlapped motion compensation and advanced collaborative filtering.

[BibT_eX]

[DOI]

Tae Hwan Lee

Byung Cheol Song

J. Electronic Imaging, 2012

A 10Gb/s adaptive equalizer with ISI level measurement.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2012

A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International SOC Conference, 2012

A high-speed adaptive linear equalizer with ISI level detection using periodic training pattern.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

An audio clock regenerator with a wide dividing ratio for HDMI.

[BibT_eX]

[DOI]

Seung-Wuk Oh

Sang-Ho Kim

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A non-coherent BPSK receiver with dual band filtering for implantable biomedical devices.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement.

[BibT_eX]

[DOI]

Tae-Ho Kim

Yong-Hwan Moon

IEICE Trans. Electron., 2011

Way-lookup buffer for low-power set-associative cache.

[BibT_eX]

[DOI]

Sungjae Lee

Inhwan Lee

IEICE Electron. Express, 2011

Low-power non-coherent data and power recovery circuit for implantable biomedical devices.

[BibT_eX]

[DOI]

Tae-Ho Kim

Proceedings of the International SoC Design Conference, 2011

A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement.

[BibT_eX]

[DOI]

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010

SSCG with Hershey-Kiss modulation profile using Dual Sigma-Delta modulators.

[BibT_eX]

[DOI]

Hyung-Min Park

Hyun-Bae Jin

IEICE Electron. Express, 2010

A DLL-based Clock Data Recovery with a modified input format.

[BibT_eX]

[DOI]

Tae-Ho Kim

Sang-Ho Kim

IEICE Electron. Express, 2010

A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009

A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008

High-speed 8B/10B encoder design using a simplified coding table.

[BibT_eX]

[DOI]

Yong-Woo Kim

Beomseok Shin

IEICE Electron. Express, 2008

An 8B/10B encoder with a modified coding table.

[BibT_eX]

[DOI]

Yong-Woo Kim

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2005

3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling.

[BibT_eX]

[DOI]

Sung-Sop Lee

Hyung-Wook Jang

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A clock recovery circuit using half-rate 4×-oversampling PD.

[BibT_eX]

[DOI]

Hyung-Wook Jang

Sung-Sop Lee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2002

A real time image processor for reproduction of gray levels in dark areas on plasma display panel (PDP).

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2002

2001

A CMOS clock and data recovery with two-XOR phase-frequency detector circuit.

[BibT_eX]

[DOI]

Dong-Hee Kim

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1997

A CMOS high-speed data recovery circuit using the matched delay sampling technique.

[BibT_eX]

[DOI]