Lex A. Akers

According to our database1, Lex A. Akers authored at least 16 papers between 1983 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Awards

IEEE Fellow

IEEE Fellow 1997, "For contributions to analog neural networks and to the modeling of microelectronic devices.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

1996
An Electronic Habituation Chip.
J. Circuits Syst. Comput., 1996

Silicon models of visual cortical processing.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

A programmable Gaussian node.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

VLSI implementation of rehabituation.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

1995
Hardware Implementation of Habituation.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
A Temporal Neural System.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Pattern Recognition and System Control with a Neural Processor.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
An adaptive neural processing node.
IEEE Trans. Neural Networks, 1993

A neural processing node with on-chip learning.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1990
VLSI Implementation of Neural Classifiers.
Neural Comput., 1990

A retinomorphic VLSI smart sensor for invariant geometric object recognition.
Proceedings of the IJCNN 1990, 1990

TRELIS: an optimal unsupervised local training rule.
Proceedings of the IJCNN 1990, 1990

1989
A CMOS neural network for pattern association.
IEEE Micro, 1989

1988
Training a Limited-Interconnect, Synthetic Neural IC.
Proceedings of the Advances in Neural Information Processing Systems 1, 1988

A limited-interconnect synthetic neural IC.
Proceedings of International Conference on Neural Networks (ICNN'88), 1988

1983
Logic Partitioning for Minimizing Gate Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983


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