Liang Zhang

Affiliations:
  • Cadence Design Systems, Inc., San Jose, USA
  • Virginia Tech, Blacksburg, VA, USA (former)


According to our database1, Liang Zhang authored at least 7 papers between 2003 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2006
A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005
Design Verification for Sequential Systems at Various Abstraction Levels.
PhD thesis, 2005

Dynamic abstraction using SAT-based BMC.
Proceedings of the 42nd Design Automation Conference, 2005

Interleaved Invariant Checking with Dynamic Abstraction.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004
Incremental deductive & inductive reasoning for SAT-based bounded model checking.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
Efficient Sequential ATPG for Functional RTL Circuits.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Automatic Design Validation Framework for HDL Descriptions via RTL ATPG.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003


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