Indradeep Ghosh

According to our database, Indradeep Ghosh authored at least 50 papers between 1994 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Scaling Vehicle Routing Problem Solvers with QUBO-based Specialized Hardware.

Hanjing Xu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh

Proceedings of the 7th IEEE/ACM Symposium on Edge Computing, 2022

Towards Practical Explainability with Cluster Descriptors.

Xiaoyuan Liu, Ilya Tyagin, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro

Proceedings of the IEEE International Conference on Data Mining Workshops, 2022

Partitioning Dense Graphs with Hardware Accelerators.

Xiaoyuan Liu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro

Proceedings of the Computational Science - ICCS 2022, 2022

2021

Ising-Based Louvain Method: Clustering Large Graphs with Specialized Hardware.

Pouya Rezazadeh Kalehbasti, Hayato Ushijima-Mwesigwa, Avradip Mandal, Indradeep Ghosh

Proceedings of the Advances in Intelligent Data Analysis XIX, 2021

2020

Binary Matrix Factorization on Special Purpose Hardware.

Osman Asif Malik, Hayato Ushijima-Mwesigwa, Arnab Roy, Avradip Mandal, Indradeep Ghosh

CoRR, 2020

2017

KLOVER: Automatic Test Generation for C and C Programs, Using Symbolic Execution.

Hiroaki Yoshida, Guodong Li, Takuki Kamiya, Indradeep Ghosh, Sreeranga P. Rajan, Susumu Tokumoto, Kazuki Munakata, Tadahiro Uehara

IEEE Softw., 2017

2016

FSX: a tool for fine-grained incremental unit test generation for C/C++ programs.

Hiroaki Yoshida, Susumu Tokumoto, Mukul R. Prasad, Indradeep Ghosh, Tadahiro Uehara

Proceedings of the 24th ACM SIGSOFT International Symposium on Foundations of Software Engineering, 2016

FSX: fine-grained incremental unit test generation for C/C++ programs.

Hiroaki Yoshida, Susumu Tokumoto, Mukul R. Prasad, Indradeep Ghosh, Tadahiro Uehara

Proceedings of the 25th International Symposium on Software Testing and Analysis, 2016

2015

Generating Succinct Test Cases Using Don't Care Analysis.

Cuong Nguyen, Hiroaki Yoshida, Mukul R. Prasad, Indradeep Ghosh, Koushik Sen

Proceedings of the 8th IEEE International Conference on Software Testing, 2015

2014

SymJS: automatic symbolic testing of JavaScript web applications.

Guodong Li, Esben Andreasen, Indradeep Ghosh

Proceedings of the 22nd ACM SIGSOFT International Symposium on Foundations of Software Engineering, (FSE-22), Hong Kong, China, November 16, 2014

2013

JST: an automatic test generation tool for industrial Java applications with strings.

Indradeep Ghosh, Nastaran Shafiei, Guodong Li, Wei-Fan Chiang

Proceedings of the 35th International Conference on Software Engineering, 2013

Lazy Symbolic Execution through Abstraction and Sub-space Search.

Guodong Li, Indradeep Ghosh

Proceedings of the Hardware and Software: Verification and Testing, 2013

PASS: String Solving with Parameterized Array and Interval Automaton.

Guodong Li, Indradeep Ghosh

Proceedings of the Hardware and Software: Verification and Testing, 2013

2012

GKLEE: concolic verification and test generation for GPUs.

Guodong Li, Peng Li, Geoffrey Sawaya, Ganesh Gopalakrishnan, Indradeep Ghosh, Sreeranga P. Rajan

Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012

2011

KLOVER: A Symbolic Execution and Automatic Test Generation Tool for C++ Programs.

Guodong Li, Indradeep Ghosh, Sreeranga P. Rajan

Proceedings of the Computer Aided Verification - 23rd International Conference, 2011

2009

WEAVE: WEb Applications Validation Environment.

Sreeranga P. Rajan, Oksana Tkachuk, Mukul R. Prasad, Indradeep Ghosh, Nitin Goel, Tadahiro Uehara

Proceedings of the 31st International Conference on Software Engineering, 2009

2008

Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution.

Xin Li, Daryl Shannon, Indradeep Ghosh, Mizuhito Ogawa, Sreeranga P. Rajan, Sarfraz Khurshid

Proceedings of the Programming Languages and Systems, 6th Asian Symposium, 2008

Verification Techniques for System-Level Design.

Masahiro Fujita, Indradeep Ghosh, Mukul R. Prasad

The Morgan Kaufmann series in systems on silicon, Morgan Kaufmann, ISBN: 978-0-12-370616-4, 2008

2006

A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage.

Liang Zhang, Indradeep Ghosh, Michael S. Hsiao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Technique for Estimating the Difficulty of a Formal Verification Problem.

Indradeep Ghosh, Mukul R. Prasad

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

High Level Test Generation for Custom Hardware: An Industrial Perspective.

Indradeep Ghosh

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

High Level Design Validation: Current Practices and Future Directions.

Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

Efficient Sequential ATPG for Functional RTL Circuits.

Liang Zhang, Indradeep Ghosh, Michael S. Hsiao

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Precomputation-based Guarding for Dynamic and Leakage Power Reduction.

Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

On automatic generation of RTL validation test benches using circuit testing techniques.

Indradeep Ghosh, Srivaths Ravi

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Automatic Design Validation Framework for HDL Descriptions via RTL ATPG.

Liang Zhang, Michael S. Hsiao, Indradeep Ghosh

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Event-driven observability enhanced coverage analysis of C programs for functional validation.

Farzan Fallah, Indradeep Ghosh, Masahiro Fujita

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Design for Verification at the Register Transfer Level.

Indradeep Ghosh, Krishna Sekar, Vamsi Boppana

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences.

Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams.

Indradeep Ghosh, Masahiro Fujita

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Observability enhanced coverage analysis of C programs for functional validation.

Farzan Fallah, Indradeep Ghosh

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

2000

A BIST scheme for RTL circuits based on symbolic testabilityanalysis.

Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A fast and low-cost testing technique for core-based system-chips.

Indradeep Ghosh, Sujit Dey, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Hierarchical Error Diagnosis Targeting RTL Circuits.

Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A Technique for Identifying RTL and Gate-Level Correspondences.

Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Automatic test pattern generation for functional RTL circuits using assignment decision diagrams.

Indradeep Ghosh, Masahiro Fujita

Proceedings of the 37th Conference on Design Automation, 2000

1999

Hierarchical test generation and design for testability methods for ASPPs and ASIPs.

Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A low overhead design for testability and test generation technique for core-based systems-on-a-chip.

Indradeep Ghosh, Niraj K. Jha, Sujit Dey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998

A design-for-testability technique for register-transfer level circuits using control/data flow extraction.

Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

High-level test synthesis: a survey.

Indradeep Ghosh, Niraj K. Jha

Integr., 1998

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.

Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey

J. Electron. Test., 1998

A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.

Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik

Proceedings of the 35th Conference on Design Automation, 1998

A Fast and Low Cost Testing Technique for Core-Based System-on-Chip.

Indradeep Ghosh, Sujit Dey, Niraj K. Jha

Proceedings of the 35th Conference on Design Automation, 1998

1997

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.

Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits.

Sudipta Bhawmik, Indradeep Ghosh

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems.

Indradeep Ghosh, Niraj K. Jha, Sujit Dey

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs.

Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha

Proceedings of the 34st Conference on Design Automation, 1997

1996

A design for testability technique for RTL circuits using control/data flow extraction.

Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

VLSI Implementation of An Efficient ASIC Architecture for Real-Time Rotation of Digital Images.

Indradeep Ghosh, Bandana Majumdar

Int. J. Pattern Recognit. Artif. Intell., 1995

1994

Design of an Application Specific VLSI Chip for Image Rotation.

Indradeep Ghosh, Bandana Majumdar

Proceedings of the Seventh International Conference on VLSI Design, 1994