Feng Zhang
Orcid: 0000-0003-2316-0392Affiliations:
- Chinese Academy of Sciences, Institute of Microelectronics, Beijing, China
- Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China (2005 - 2010)
- Chinese Academy of Sciences, Institute of Microelectronics, Beijing, China (PhD 2005)
According to our database1,
Feng Zhang
authored at least 41 papers
between 2006 and 2024.
Collaborative distances:
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Bibliography
2024
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
P<sup>3</sup> ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference.
IEEE J. Solid State Circuits, October, 2023
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection.
Sensors, 2022
2021
Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Investigation of weight updating modes on oxide-based resistive switching memory synapse towards neuromorphic computing applications.
Sci. China Inf. Sci., 2021
24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m<sup>2</sup> Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
A 108 F<sup>2</sup>/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise.
IEEE Trans. Circuits Syst., 2020
A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm<sup>2</sup> using Sneaking Current Suppression and Compensation Techniques.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
CoRR, 2019
A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond.
CoRR, 2019
Proceedings of the 16th International Conference on Synthesis, 2019
A Modeling Approach for 7nm Technology Node Area-Consuming Circuit Optimization and Beyond.
Proceedings of the 16th International Conference on Synthesis, 2019
Particle Swarm Optimization for Great Enhancement in Semi-supervised Retinal Vessel Segmentation with Generative Adversarial Networks.
Proceedings of the Machine Learning and Medical Engineering for Cardiovascular Health and Intravascular Imaging and Computer Assisted Stenting, 2019
Proceedings of the 23rd IEEE International Conference on Computer Supported Cooperative Work in Design, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Wide-range tracking technique for process-variation-robust clock and data recovery applications.
Frontiers Inf. Technol. Electron. Eng., 2017
A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
A 128 Kb HfO<sub>2</sub> ReRAM with Novel Double-Reference and Dynamic-Tracking scheme for write yield improvement.
IEICE Electron. Express, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
A PVT variation tolerant and low power 5Gb/s clock and data recovery circuit for PCI-E 2.0/USB 3.0.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012
A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
A novel SST transmitter with mutually decoupled impedance self-calibration and equalization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
2006
A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006