Siyu Liao
Orcid: 0000-0001-5709-3015
According to our database1,
Siyu Liao
authored at least 33 papers
between 2017 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Unsupervised Wireless Diarization: A Potential New Attack on Encrypted Wireless Networks.
Proceedings of the IEEE International Conference on Communications, 2023
Proceedings of the 32nd ACM International Conference on Information and Knowledge Management, 2023
Capacity Gain from Multi-Mode Reconfigurable Antennas as a Function of Degrees of Control in Clustered MIMO Channels.
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023
2022
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022
2021
PermCNN: Energy-Efficient Convolutional Neural Network Hardware Architecture With Permuted Diagonal Structure.
IEEE Trans. Computers, 2021
GoSPA: An Energy-efficient High-performance Globally Optimized SParse Convolutional Neural Network Accelerator.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Algorithm and Hardware Co-design for Deep Learning-powered Channel Decoder: A Case Study.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Towards Efficient Tensor Decomposition-Based DNN Model Compression With Optimization Framework.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021
Towards Extremely Compact RNNs for Video Recognition With Fully Decomposed Hierarchical Tucker Structure.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021
Doubly Residual Neural Decoder: Towards Low-Complexity High-Performance Channel Decoding.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021
2020
Compressing Recurrent Neural Networks Using Hierarchical Tucker Tensor Decomposition.
CoRR, 2020
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
CAG: A Real-Time Low-Cost Enhanced-Robustness High-Transferability Content-Aware Adversarial Attack Generator.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020
2019
IEEE Trans. Sustain. Comput., 2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Compressing Deep Neural Networks Using Toeplitz Matrix: Algorithm Design and Fpga Implementation.
Proceedings of the IEEE International Conference on Acoustics, 2019
Reduced-complexity Deep Neural Network-aided Channel Code Decoder: A Case Study for BCH Decoder.
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019
2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
Towards Ultra-High Performance and Energy Efficiency of Deep Learning Systems: An Algorithm-Hardware Co-Optimization Framework.
Proceedings of the Thirty-Second AAAI Conference on Artificial Intelligence, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
CirCNN: Accelerating and Compressing Deep Neural Networks Using Block-CirculantWeight Matrices.
CoRR, 2017
Theoretical Properties for Neural Networks with Weight Matrices of Low Displacement Rank.
CoRR, 2017
CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Theoretical Properties for Neural Networks with Weight Matrices of Low Displacement Rank.
Proceedings of the 34th International Conference on Machine Learning, 2017
Energy-efficient, high-performance, highly-compressed deep neural network design using block-circulant matrices.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017