Liuting Shang

According to our database, Liuting Shang authored at least 12 papers between 2018 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Novel FPGA Technology Mapping for Dual-Output LUTs: Methodology and Application.

Liuting Shang, Sheng Lu, Sungyong Jung, Qilian Liang, Chenyun Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2026

Memristor-Based Spiking Neural Network Accelerator for Bio-inspired Interception Task.

Qianhou Qu, Sheng Lu, Liuting Shang, Jaihan Utailawon, Sungyong Jung, Qilian Liang, Chenyun Pan

CoRR, May, 2026

2025

Technology/System Co-Optimization for FPGA Using Emerging Reconfigurable Logic Device.

Sheng Lu, Liuting Shang, Sungyong Jung, Yichen Zhang, Qilian Liang, Chenyun Pan

ACM J. Emerg. Technol. Comput. Syst., July, 2025

A Novel RFET-Based FPGA Architecture Based on Delay-Aware Packing Algorithm.

Sheng Lu, Liuting Shang, Sungyong Jung, Qilian Liang, Chenyun Pan

IEEE Trans. Emerg. Top. Comput., 2025

Graphene-Based FPGA Design and Optimization at the 7nm FinFET Technology Node.

Sheng Lu, Zhenlin Pei, Liuting Shang, Sungyong Jung, Qilian Liang, Chenyun Pan

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

2024

A Novel Delay-Aware Packing Algorithm for FPGA Architecture Using RFET.

Sheng Lu, Liuting Shang, Sungyong Jung, Yichen Zhang, Chenyun Pan

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Emerging Reconfigurable Logic Device Based FPGA Design and Optimization.

Sheng Lu, Liuting Shang, Sungyong Jung, Chenyun Pan

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023

Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis.

Liuting Shang, Azad Naeemi, Chenyun Pan

IEEE Open J. Comput. Soc., 2023

Novel Fence Generation Methods for Accelerating Reconfigurable Exact Synthesis.

Liuting Shang, Sheng Lu, Sungyong Jung, Chenyun Pan

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices.

Sheng Lu, Zhenlin Pei, Liuting Shang, Sungyong Jung, Chenyun Pan

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2020

Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator.

Liuting Shang, Muhammad Adil, Ramtin Madani, Chenyun Pan

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2018

SRMC: A Multibit Memristor Crossbar for Self-Renewing Image Mask.

Liuting Shang, Shukai Duan, Lidan Wang, Tingwen Huang

IEEE Trans. Very Large Scale Integr. Syst., 2018