Zhenlin Pei

According to our database, Zhenlin Pei authored at least 11 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Reliability-Driven Sneak Path Current Modeling and Optimization for Passive Memristor Crossbar Arrays.

Zhenlin Pei, Shah Zayed Riam, Kyle Mooney, Chenyun Pan, Na Gong, Jinhui Wang

Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

2025

Sneak Path Current Modeling in Memristor Crossbar Arrays for Analog In-Memory Computing.

Shah Zayed Riam, Zhenlin Pei, Kyle Mooney, Chenyun Pan, Na Gong, Jinhui Wang

CoRR, November, 2025

Interconnect/Memory Co-Design and Co-Optimization Using Differential Transmission Lines.

Zhenlin Pei, Hsiao-Hsuan Liu, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Prashant Dubey, Chenyun Pan

IEEE Trans. Very Large Scale Integr. Syst., 2025

System Scenario-Based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes.

Mahta Mayahinia, Tommaso Marinelli, Zhenlin Pei, Hsiao-Hsuan Liu, Chenyun Pan, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori

ACM Trans. Embed. Comput. Syst., 2025

Graphene-Based FPGA Design and Optimization at the 7nm FinFET Technology Node.

Sheng Lu, Zhenlin Pei, Liuting Shang, Sungyong Jung, Qilian Liang, Chenyun Pan

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

2024

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect.

Hsiao-Hsuan Liu, Carlo Gilardi, Shairfe Muhammad Salahuddin, Zhenlin Pei, Pieter Schuddinck, Yang Xiang, Pieter Weckx, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert, Chenyun Pan, Subhasish Mitra, Francky Catthoor

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes.

Mahta Mayahinia, Tommaso Marinelli, Zhenlin Pei, Hsiao-Hsuan Liu, Chenyun Pan, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori

IEEE Embed. Syst. Lett., December, 2024

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus.

Zhenlin Pei, Hsiao-Hsuan Liu, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Dawit Burusie Abdi, James Myers, Chenyun Pan

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024

2023

A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices.

Sheng Lu, Zhenlin Pei, Liuting Shang, Sungyong Jung, Chenyun Pan

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access.

Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Shairfe Muhammad Salahuddin, Francky Catthoor, Zsolt Tokei, Chenyun Pan

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect.

Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Chenyun Pan

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023