Azad Naeemi

According to our database1, Azad Naeemi authored at least 45 papers between 2006 and 2021.

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Bibliography

2021
Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits.
CoRR, 2021

2020
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper).
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
A Mixed Signal Architecture for Convolutional Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2019

Beyond Motivation and Memorization: Fostering Scientific Inquiry with Games.
Proceedings of the Extended Abstracts of the Annual Symposium on Computer-Human Interaction in Play Companion Extended Abstracts, 2019

2018
Particle in a Box: An Experiential Environment for Learning Introductory Quantum Mechanics.
IEEE Trans. Educ., 2018

Generic system-level modeling and optimization for beyond CMOS device applications.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule.
Proceedings of the 55th Annual Design Automation Conference, 2018

Hybrid piezoelectric-magnetic neurons: a proposal for energy-efficient machine learning.
Proceedings of the ACMSE 2018 Conference, Richmond, KY, USA, March 29-31, 2018, 2018

2017
Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation.
CoRR, 2017

Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications.
CoRR, 2017

Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Non-volatile spin wave majority gate at the nanoscale.
CoRR, 2016

A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices.
CoRR, 2016

Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls.
CoRR, 2016

Impact of interconnect variability on circuit performance in advanced technology nodes.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Performance modeling and optimization for on-chip interconnects in 3D memory arrays.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Device/system performance modeling of stacked lateral NWFET logic.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015
A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition.
CoRR, 2015

Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014
Wiring resource minimization for physically-complex Network-on-Chip architectures.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Pipeline design in spintronic circuits.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

An analytical approach to system-level variation analysis and optimization for multi-core processor.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Interactive visualizations for teaching quantum mechanics and semiconductor physics.
Proceedings of the IEEE Frontiers in Education Conference, 2014

BEOL Scaling Limits and Next Generation Technology Prospects.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Evaluation of the Potential Performance of Graphene Nanoribbons as On-Chip Interconnects.
Proc. IEEE, 2013

Performance modeling for interconnects for conventional and emerging switches.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Device- and system-level performance modeling for graphene P-N junction logic.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Power Aware Post-manufacture Tuning of Analog Nanocircuits.
Proceedings of the 16th European Test Symposium, 2011

2010
Nanoelectronics in retrospect, prospect and principle.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
Physical models for electron transport in graphene nanoribbons and their junctions.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Carbon nanotube interconnects.
Proceedings of the 2007 International Symposium on Physical Design, 2007

IntSim: A CAD tool for optimization of multilevel interconnect networks.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects.
Proceedings of the 44th Design Automation Conference, 2007

Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006


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