Azad Naeemi
Orcid: 0000-0003-4774-9046
According to our database1,
Azad Naeemi
authored at least 49 papers
between 2006 and 2024.
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Bibliography
2024
Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search.
CoRR, 2024
2023
Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis.
IEEE Open J. Comput. Soc., 2023
2022
Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators.
Proceedings of the IEEE International Memory Workshop, 2022
2021
2020
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper).
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
ACM J. Emerg. Technol. Comput. Syst., 2019
Proceedings of the Extended Abstracts of the Annual Symposium on Computer-Human Interaction in Play Companion Extended Abstracts, 2019
2018
Particle in a Box: An Experiential Environment for Learning Introductory Quantum Mechanics.
IEEE Trans. Educ., 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule.
Proceedings of the 55th Annual Design Automation Conference, 2018
Hybrid piezoelectric-magnetic neurons: a proposal for energy-efficient machine learning.
Proceedings of the ACMSE 2018 Conference, Richmond, KY, USA, March 29-31, 2018, 2018
2017
CoRR, 2017
CoRR, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
CoRR, 2016
Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls.
CoRR, 2016
Impact of interconnect variability on circuit performance in advanced technology nodes.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
2015
A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition.
CoRR, 2015
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
An analytical approach to system-level variation analysis and optimization for multi-core processor.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the IEEE Frontiers in Education Conference, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Evaluation of the Potential Performance of Graphene Nanoribbons as On-Chip Interconnects.
Proc. IEEE, 2013
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices.
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
2011
Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 16th European Test Symposium, 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 2007 International Symposium on Physical Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects.
Proceedings of the 44th Design Automation Conference, 2007
Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006