Luca Crippa

According to our database, Luca Crippa authored at least 11 papers between 2001 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Leveraging Large-Scale TLC 3D NAND Flash Characterization to Investigate Early Lifetime Reliability of SSDs through Extreme Value Statistics.

Rino Micheloni, Luca Crippa, Alessia Marelli, Lorenzo Zuolo, Piero Olivo, Cristian Zambelli

Proceedings of the IEEE International Reliability Physics Symposium, 2025

2021

A Serverless Cloud Integration For Quantum Computing.

Michele Grossi, Luca Crippa, Antonello Aita, Giacomo Bartoli, Vito Sammarco, Eleonora Picca, N. Said, Filippo Tramonto, Federico Mattei

CoRR, 2021

2017

Array Architectures for 3-D NAND Flash Memories.

Rino Micheloni, Seiichi Aritome, Luca Crippa

Proc. IEEE, 2017

Architectural and Integration Options for 3D NAND Flash Memories.

Rino Micheloni, Luca Crippa, Cristian Zambelli, Piero Olivo

Comput., 2017

2016

3D Floating Gate NAND Flash Memories.

Rino Micheloni, Luca Crippa

Proceedings of the 3D Flash Memories, 2016

3D Stacked NAND Flash Memories.

Rino Micheloni, Luca Crippa

Proceedings of the 3D Flash Memories, 2016

Advanced Architectures for 3D NAND Flash Memories with Vertical Channel.

Luca Crippa, Rino Micheloni

Proceedings of the 3D Flash Memories, 2016

3D Charge Trap NAND Flash Memories.

Luca Crippa, Rino Micheloni

Proceedings of the 3D Flash Memories, 2016

2006

A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput.

Rino Micheloni, R. Ravasio, Alessia Marelli, E. Alice, V. Altieri, A. Bovino, Luca Crippa, E. Di Martino, L. D'Onofrio, A. Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, Ilaria Motta, A. Prisco, Giancarlo Ragone, M. Romano, Miriam Sangalli, P. Sauro, Marco Scotti, S. Won

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003

The flash memory read path: building blocks and critical aspects.

Rino Micheloni, Luca Crippa, Miriam Sangalli, Giovanni Campardo

Proc. IEEE, 2003

2001

Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices.

Andrea Silvagni, Stefano Zanardi, Alessandro Manstretta, Marco Scotti, Luca Crippa, Giancarlo Ragone, Giuseppe Fusillo, Giovanni Campardo, Osama Khouri, Marcello Stefanelli

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001