Giovanni Campardo

According to our database1, Giovanni Campardo authored at least 11 papers between 2000 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
Signal Integrity Flow for System-in-Package and Package-on-Package Devices.
Proc. IEEE, 2009

SoC and SiP, the Yin and Yang of the Tao for the New Electronic Era.
Proc. IEEE, 2009

2008
A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Risks for Signal Integrity in System in Package and Possible Remedies.
Proceedings of the 13th European Test Symposium, 2008

2007
A Reduced Output Ringing CMOS Buffer.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

2003
The flash memory read path: building blocks and critical aspects.
Proc. IEEE, 2003

An overview of flash architectural developments.
Proc. IEEE, 2003

2001
Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
40-mm<sup>2</sup> 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory.
IEEE J. Solid State Circuits, 2000

Hierarchical Sector Biasing Organization for Flash Memories.
Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

Program word-line voltage generator for multilevel flash memories.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000


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