Piero Olivo

Orcid: 0000-0002-8751-4666

According to our database1, Piero Olivo authored at least 67 papers between 1988 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Experimental verification and benchmark of in-memory principal component analysis by crosspoint arrays of resistive switching memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
Optimized programming algorithms for multilevel RRAM in hardware neural networks.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2019
LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives.
IEEE Trans. Emerg. Top. Comput., 2019

Enabling Computational Storage Through FPGA Neural Network Accelerator for Enterprise SSD.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Reliability of CMOS Integrated Memristive HfO2 Arrays with Respect to Neuromorphic Computing.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Low-energy inference machine with multilevel HfO2 RRAM arrays.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2018
Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018

An Automated Test Equipment for Characterization of Emerging MRAM and RRAM Arrays.
IEEE Trans. Emerg. Top. Comput., 2018

Is Consumer Electronics Redesigning Our Cars?: Challenges of Integrated Technologies for Sensing, Computing, and Storage.
IEEE Consumer Electron. Mag., 2018

Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs.
Proceedings of the 2018 New Generation of CAS, 2018

2017
Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance.
Proc. IEEE, 2017

Solid-State Drives (SSDs) [Scanning the Issue].
Proc. IEEE, 2017

Architectural and Integration Options for 3D NAND Flash Memories.
Comput., 2017

2016
Reliability of 3D NAND Flash Memories.
Proceedings of the 3D Flash Memories, 2016

2015
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers.
ACM Trans. Embed. Comput. Syst., 2015

SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Design space exploration of latency and bandwidth in RRAM-based solid state drives.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Reliability and cell-to-cell variability of TAS-MRAM arrays under cycling conditions.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

RRAM Reliability/Performance Characterization through Array Architectures Investigations.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Automated characterization of TAS-MRAM test arrays.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014
FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories.
ACM Trans. Archit. Code Optim., 2014

SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems.
Proceedings of the 2013 International Symposium on System on Chip, 2013

2012
Modeling of SET seasoning effects in Phase Change Memory arrays.
Microelectron. Reliab., 2012

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Nonvolatile Memory Partitioning Scheme for Technology-Based Performance-Reliability Tradeoff.
IEEE Embed. Syst. Lett., 2011

2006
Improving performance and reliability of NOR-Flash arrays by using pulsed operation.
Microelectron. Reliab., 2006

2005
Reliability of erasing operation in NOR-Flash memories.
Microelectron. Reliab., 2005

2003
Overerase phenomena: an insight into flash memory reliability.
Proc. IEEE, 2003

2001
Automated test equipment for research on nonvolatile memories.
IEEE Trans. Instrum. Meas., 2001

1998
A Bist Scheme for Non-Volatile Memories.
J. Electron. Test., 1998

1997
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Flash memory cells-an overview.
Proc. IEEE, 1997

1996
Modeling and simulation of broken connections in CMOS IC's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Self-Learning Signature Analysis for Non-Volatile Memory Testing.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults.
J. Electron. Test., 1995

Test pattern generation for I<sub>DDQ</sub>: increasing test quality.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Reliability evaluation of combinational logic circuits by symbolic simulation.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Correlation between I<sub>DDQ</sub> testing quality and sensor accuracy.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Modeling of Broken Connections Faults in CMOS ICs.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Analysis of resistive bridging fault detection in BiCMOS digital ICs.
IEEE Trans. Very Large Scale Integr. Syst., 1993

Fault simulation of parametric bridging faults in CMOS IC's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

A Highly Testable 1-out-of-3 CMOS Checker.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
A probabilistic fault model for 'analog' faults in digital CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Testability measures in pseudorandom testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Dynamic effects in the detection of bridging faults in CMOS ICs.
J. Electron. Test., 1992

CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
A novel critical path heuristic for fast fault grading.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Fault simulation of unconventional faults in CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Analysis and Design of Linear Finite State Machines for Signature Analysis Testing.
IEEE Trans. Computers, 1991

Fault simulation for general FCMOS ICs.
J. Electron. Test., 1991

A probabilistic fault model for analog faults.
Proceedings of the conference on European design automation, 1991

Detection of PLA multiple crosspoint faults.
Proceedings of the conference on European design automation, 1991

1990
Aliasing in signature analysis testing with multiple input shift registers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Testing of E<sup>2</sup>PROM aging and endurance: A case study.
Eur. Trans. Telecommun., 1990

1989
An analytical model for the aliasing probability in signature analysis testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing.
Proceedings of the Proceedings International Test Conference 1989, 1989

A Testing Technique to Characterize E^2PROM's Aging and Endurance.
Proceedings of the Proceedings International Test Conference 1989, 1989

CMOS Design for Improved IC Testability.
Proceedings of the Proceedings International Test Conference 1989, 1989

Improved testability evaluations in combinational logic networks.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988
Aliasing errors in signature analysis testing of integrated circuits.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988


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