Luis Fernando González Pérez

According to our database, Luis Fernando González Pérez authored at least 10 papers between 2000 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

A VLSI architecture for the QR decomposition based on the MCGR algorithm.

Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

2012

A VLSI architecture for the K-best Sphere-Decoder in MIMO systems.

Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

2011

Design and Implementation of a Simplified Turbo Decoder for 3GPP2.

Lennin C. Yllescas-Calderon, Adrian J. Espino-Orozco, Ramón Parra-Michel, Luis Fernando González Pérez

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Analysis of Parallel Sorting Algorithms in K-best Sphere-Decoder Architectures for MIMO Systems.

Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2006

Improving Least-Squares-Based VBLAST Architecture with Conventional Channel Coding.

Karina Sosa, Luis Fernando González Pérez, Miguel Bazdresch, Jorgue Rodriguez-Guisantes

Proceedings of the 16th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2006), 27 February 2005, 2006

2005

Performance Study of Space-Time Communications Systems Based on the VBLAST Algorithm.

Karina Sosa, Luis Fernando González Pérez, Miguel Bazdresch, Jorgue Rodriguez-Guisantes

Proceedings of the 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005, 2005

VLSI Architecture for the M Algorithm Suited for Detection and Source Coding Applications.

Luis Fernando González Pérez, Emmanuel Boutillon, Andrés David García García, Javier Eduardo González Villarruel, Reynaldo Félix Acuña

Proceedings of the 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005, 2005

Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA.

Roberto Ramírez Marín, Andrés David García García, Luis Fernando González Pérez, Javier Eduardo González Villarruel

Proceedings of the 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005, 2005

Power Consumption Management on FPGAs.

Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña

Proceedings of the 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005, 2005

2000

A study of a suboptimal VLSI architecture for joint source-channel trellis coding.

Luis Fernando González Pérez, Emmanuel Boutillon

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000