Andrés David García García

According to our database, Andrés David García García authored at least 12 papers between 1999 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2013

A VLSI architecture for the QR decomposition based on the MCGR algorithm.

Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

2012

A VLSI architecture for the K-best Sphere-Decoder in MIMO systems.

Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

2011

Analysis of Parallel Sorting Algorithms in K-best Sphere-Decoder Architectures for MIMO Systems.

Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010

Multi-channel Driving Systems for Therapeutic Applications Based-on Focused Ultrasound.

J. Pindter-Medina, Samuel Pichardo, Laura Curiel, Andrés David García García, Jesús Enrique Chong-Quero

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

2006

Bio - Inspired & Traditional Approaches to Obtain Fault Tolerance.

Carlos E. Gutiérrez Salmeron, Andrés David García García, Reynaldo Félix Acuña

Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

Measuring Leakage Power in Nanometer CMOS 6T-SRAM Cells.

Marcos R. de Alba-Rosano, Andrés David García García

Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

2005

VLSI Architecture for the M Algorithm Suited for Detection and Source Coding Applications.

Luis Fernando González Pérez, Emmanuel Boutillon, Andrés David García García, Javier Eduardo González Villarruel, Reynaldo Félix Acuña

Proceedings of the 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005, 2005

Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA.

Roberto Ramírez Marín, Andrés David García García, Luis Fernando González Pérez, Javier Eduardo González Villarruel

Proceedings of the 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005, 2005

Power Consumption Management on FPGAs.

Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña

Proceedings of the 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005, 2005

2000

Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption.

Andrés D. García, Wayne P. Burleson, Jean-Luc Danger

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption.

Andrés D. García, Jean-Luc Danger, Wayne P. Burleson

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

1999

Power Modelling in Field Programmable Gate Arrays (FPGA).

Andrés D. García, Wayne P. Burleson, Jean-Luc Danger

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999