M. R. Ashuthosh

According to our database, M. R. Ashuthosh authored at least 5 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

MATANALYZE - A Custom Accelerator Generator for Sparse × Dense and Dense × Sparse Matrix Multiplication.

Mohammed Sahel, Disha Kiran D, M. R. Ashuthosh, Madhura Purnaprajna

Proceedings of the 32nd IEEE International Conference on High Performance Computing, Data and Analytics, HiPC 2025, 2025

PARISCV: A RISC-V Profiler for Application-Specific Hardware Optimization.

Spoorthi S, M. R. Ashuthosh, Bharadhwaj K, Vinay Reddy, Madhura Purnaprajna

Proceedings of the 32nd IEEE International Conference on High Performance Computing, Data and Analytics, HiPC 2025, 2025

2023

Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders.

Srinivasan Subramaniyan, Oscar Ferraz, M. R. Ashuthosh, Santosh Krishna, Guohui Wang, Joseph R. Cavallaro, Vítor Silva, Gabriel Falcão, Madhura Purnaprajna

IEEE Des. Test, February, 2023

2022

MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication.

M. R. Ashuthosh, Santosh Krishna, Vishvas Sudarshan, Srinivasan Subramaniyan, Madhura Purnaprajna

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2020

Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs.

Srinivasan Subramaniyan, Oscar Ferraz, M. R. Ashuthosh, Santosh Krishna, Guohui Wang, Joseph R. Cavallaro, Vítor Silva, Gabriel Falcão, Madhura Purnaprajna

Proceedings of the IEEE Workshop on Signal Processing Systems, 2020