Madhura Purnaprajna

According to our database1, Madhura Purnaprajna authored at least 20 papers between 2004 and 2019.

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Bibliography

2019
Recurrent Neural Networks: An Embedded Computing Perspective.
CoRR, 2019

k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

2018
TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Streaming Tiles: Flexible Implementation of Convolution Neural Networks Inference on Manycore Architectures.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Performance modeling for data distribution in heterogeneous computing systems: work in progress.
Proceedings of the International Conference on Compilers, 2018

2015
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs.
ACM Trans. Embedded Comput. Syst., 2015

Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2013
Shadow And-Inverter Cones.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
Making wide-issue VLIW processors viable on FPGAs.
TACO, 2012

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2010
Run-time reconfigurable multiprocessors.
PhD thesis, 2010

Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis.
TRETS, 2010

2009
Run-time reconfigurability in embedded multiprocessors.
SIGARCH Computer Architecture News, 2009

Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Genetic algorithms for hardware-software partitioning and optimal resource allocation.
Journal of Systems Architecture, 2007

2004
Genetic Algorithms in Hardware-Software Partitioning.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004


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