M. S. Hrishikesh

According to our database, M. S. Hrishikesh authored at least 3 papers between 2000 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2002

The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays.

M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas

Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

2001

Static Energy Reduction Techniques for Microprocessor Caches.

Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000

Clock rate versus IPC: the end of the road for conventional microarchitectures.

Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger

Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000