M. S. Hrishikesh

According to our database1, M. S. Hrishikesh authored at least 3 papers between 2000 and 2002.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2002
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

2001
Static Energy Reduction Techniques for Microprocessor Caches.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000
Clock rate versus IPC: the end of the road for conventional microarchitectures.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000


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