Norman P. Jouppi
Orcid: 0000-0003-1765-1929Affiliations:
- Google, Mountain View, CA, USA
According to our database1,
Norman P. Jouppi
authored at least 136 papers
between 1982 and 2023.
Collaborative distances:
Collaborative distances:
Awards
ACM Fellow
ACM Fellow 2006, "For contributions to the design and analysis of high-performance processors and memory systems.".
IEEE Fellow
IEEE Fellow 2003, "For contributions to the design and analysis of high performance processors and memory systems.".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on viaf.org
-
on orcid.org
-
on id.loc.gov
-
on d-nb.info
-
on dl.acm.org
On csauthors.net:
Bibliography
2023
CoRR, 2023
CoRR, 2023
Lightwave Fabrics: At-Scale Optical Circuit Switching for Datacenter and Machine Learning Systems.
Proceedings of the ACM SIGCOMM 2023 Conference, 2023
TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
A Machine Learning Supercomputer with an Optically Reconfigurable Interconnect and Embeddings Support.
Proceedings of the 35th IEEE Hot Chips Symposium, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021
2020
Proceedings of the IEEE Hot Chips 32 Symposium, 2020
2018
2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
2016
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor.
IEEE Micro, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015
2014
Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories.
ACM Trans. Archit. Code Optim., 2014
ACM Trans. Archit. Code Optim., 2014
2013
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing.
ACM Trans. Archit. Code Optim., 2013
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies.
ACM Trans. Archit. Code Optim., 2013
Proceedings of the International Conference for High Performance Computing, 2013
Kiln: closing the performance gap between systems with and without persistence support.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013
McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
i<sup>2</sup>WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
ACM Trans. Archit. Code Optim., 2012
IEEE Micro, 2012
Proceedings of the SC Conference on High Performance Computing Networking, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01734-6, 2011
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems.
ACM Trans. Archit. Code Optim., 2011
Proceedings of the Conference on High Performance Computing Networking, 2011
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Low Power Networks-on-Chip., 2011
2010
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.
Proceedings of the Conference on High Performance Computing Networking, 2010
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
2009
Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08).
SIGARCH Comput. Archit. News, 2009
Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs.
IEEE Comput. Archit. Lett., 2009
Technical perspective - Software and hardware support for deterministic replay of parallel programs.
Commun. ACM, 2009
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07).
SIGARCH Comput. Archit. News, 2008
IEEE Micro, 2008
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008
2007
Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06).
SIGARCH Comput. Archit. News, 2007
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007
Configurable isolation: building high availability systems with commodity multi-core processors.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006
Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006
Proceedings of the 2006 International Conference on Compilers, 2006
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006
2005
SIGARCH Comput. Archit. News, 2005
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05).
SIGARCH Comput. Archit. News, 2005
System-wide performance monitors and their application to the optimization of coherent memory accesses.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2005
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005
Telepresence Systems With Automatic Preservation of User Head Height, Local Rotation, and Remote Translation.
Proceedings of the 2005 IEEE International Conference on Robotics and Automation, 2005
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
2004
Proceedings of the 12th ACM International Conference on Multimedia, 2004
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004
A First Generation Mutually-Immersive Mobile Telepresence Surrogate with Automatic Backtracking.
Proceedings of the 2004 IEEE International Conference on Robotics and Automation, 2004
Region of interest editing of MPEG-2 video streams in the compressed domain.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004
2003
IEEE Comput. Archit. Lett., 2003
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
2002
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002
Proceedings of the 2002 ACM on Computer supported cooperative work video program, 2002
Proceedings of the CSCW 2002, 2002
2000
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000
Proceedings of the 2000 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, 2000
1999
Int. J. Parallel Program., 1999
Proceedings of the 26th Annual Conference on Computer Graphics and Interactive Techniques, 1999
Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999
Proceedings of the 1999 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, 1999
1998
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998
Retrospective: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998
Proceedings of the 1998 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, Lisbon, Portugal, August 31, 1998
1997
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997
Proceedings of the 24th International Symposium on Computer Architecture, 1997
Proceedings of the 24th International Symposium on Computer Architecture, 1997
1996
IEEE J. Solid State Circuits, 1996
IEEE J. Solid State Circuits, 1996
Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996
1995
How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?
Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995
1994
IEEE Micro, 1994
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994
1993
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993
1992
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992
1991
1990
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990
1989
The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance.
IEEE Trans. Computers, 1989
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
Proceedings of the ASPLOS-III Proceedings, 1989
Proceedings of the ASPLOS-III Proceedings, 1989
1988
1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987
1983
Proceedings of the 20th Design Automation Conference, 1983
1982
Proceedings of the 15th annual workshop on Microprogramming, 1982
The MIPS Machine.
Proceedings of the COMPCON'82, 1982
Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, 1982