Maher Jridi
Orcid: 0000-0002-9316-7920
According to our database1,
Maher Jridi
authored at least 29 papers
between 2006 and 2024.
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Bibliography
2024
CoRR, 2024
2023
No-Reference 3D Point Cloud Quality Assessment Using Multi-View Projection and Deep Convolutional Neural Network.
IEEE Access, 2023
Proceedings of the Management of Digital EcoSystems - 15th International Conference, 2023
Supply Chain Forecasting in a Fast-Moving Global Economy: Review, Limits and Future Directions.
Proceedings of the 28th International Conference on Automation and Computing, 2023
Proceedings of the 20th International Conference on Content-based Multimedia Indexing, 2023
2022
A multicriteria optimization of the discrete sine transform for versatile video coding standard.
Signal Image Video Process., 2022
Knowl. Based Syst., 2022
J. Real Time Image Process., 2022
Integr., 2022
Semantic Images Segmentation for Autonomous Driving Using Self-Attention Knowledge Distillation.
Proceedings of the 16th International Conference on Signal-Image Technology & Internet-Based Systems, 2022
High-speed and Low-area Implementations of a Generic and Parallel Integral Image Architecture.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the QoEVMA@MM 2022: Proceedings of the 2nd Workshop on Quality of Experience in Visual Multimedia Applications, 2022
2020
J. Real Time Image Process., 2020
2017
IEEE Trans. Circuits Syst. Video Technol., 2017
2016
FPGA implementation of improved binarizer design for context-based adaptive binary arithmetic coder.
Proceedings of the International Image Processing, Applications and Systems, 2016
2015
A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2013
Zero-quantised discrete cosine transform coefficients prediction technique for intra-frame video encoding.
IET Image Process., 2013
Proceedings of the Real-Time Image and Video Processing 2013, 2013
Proceedings of the Real-Time Image and Video Processing 2013, 2013
Evaluation and implementation of simultaneous binary arithmetic coding and encryption for HD H264/AVC codec.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013
2012
Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression.
VLSI Design, 2012
Area-Delay Efficient FFT Architecture using Parallel Processing and New Memory Sharing Technique.
J. Circuits Syst. Comput., 2012
2010
Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010
A low-power, high-speed DCT architecture for image compression: Principle and implementation.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
2008
A new orthogonal online digital calibration for time-interleaved analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Orthogonal correction implementation for time interleaved analog-to-digital converters: Realtime application.
Proceedings of the 2008 16th European Signal Processing Conference, 2008
2006
An offset and gain calibration method for time-interleaved analog to digital converters.
Proceedings of the 13th IEEE International Conference on Electronics, 2006