Pramod Kumar Meher

Affiliations:
  • C. V. Raman College of Engineering, Bhubaneswar, India
  • Nanyang Technological University, Singapore


According to our database1, Pramod Kumar Meher authored at least 180 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

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Bibliography

2023
Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023

An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023

Dense-PSP-UNet: A neural network for fast inference liver ultrasound segmentation.
Comput. Biol. Medicine, February, 2023

2022
Enhanced Sharpening of CIC Decimation Filters, Implementation and Applications.
Circuits Syst. Signal Process., 2022

Energy-Efficient High-Speed ASIC Implementation of Convolutional Neural Network Using Novel Reduced Critical-Path Design.
IEEE Access, 2022

2021
Design of Very High-Speed Pipeline FIR Filter Through Precise Critical Path Analysis.
IEEE Access, 2021

2020
Analysis and Design of Unified Architectures for Zero-Attraction-Based Sparse Adaptive Filters.
IEEE Trans. Very Large Scale Integr. Syst., 2020

An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation.
IEEE Trans. Very Large Scale Integr. Syst., 2020

An Analytical Framework and Approximation Strategy for Efficient Implementation of Distributed Arithmetic-Based Inner-Product Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Efficient approximate core transform and its reconfigurable architectures for HEVC.
J. Real Time Image Process., 2020

2019
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension Fields.
Circuits Syst. Signal Process., 2019

50 Years of FFT Algorithms and Applications.
Circuits Syst. Signal Process., 2019

Multichannel Filters for Wireless Networks: Lookup-Table-Based Efficient Implementation.
IEEE Consumer Electron. Mag., 2019

Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Low-Complexity Systolic Multiplier for GF(2<sup>m</sup>) using Toeplitz Matrix-Vector Product Method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Analysis and Design of Approximate Inner-Product Architectures Based on Distributed Arithmetic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2<sup>m</sup>) Based on Trinomials.
IEEE Trans. Multi Scale Comput. Syst., 2018

Threshold-Guided Design and Optimization for Harris Corner Detector Architecture.
IEEE Trans. Circuits Syst. Video Technol., 2018

Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form Structures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Efficient Cross-Correlation Algorithm and Architecture for Robust Synchronization in Frame-Based Communication Systems.
Circuits Syst. Signal Process., 2018

2017
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Scalable Approximate DCT Architectures for Efficient HEVC-Compliant Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2017

Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2<sup>m</sup>) Based on NIST Polynomials.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2<sup>m</sup>) Based on Irreducible All-One Polynomials.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Novel Structure for Area-Efficient Implementation of FIR Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Lookup Table-Based Low-Power Implementation of Multi-channel Filters for Software Defined Radio.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2016
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016

On Efficient Retiming of Fixed-Point Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Concept, Design, and Implementation of Reconfigurable CORDIC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Introduction of New Associate Editors.
IEEE Trans. Circuits Syst. Video Technol., 2016

Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2<sup>m</sup>) Using Generalized (a, b)-Way Karatsuba Algorithm".
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic.
Integr., 2016

Seamless Pipelining of DSP Circuits.
Circuits Syst. Signal Process., 2016

2015
FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction.
IEEE Trans. Very Large Scale Integr. Syst., 2015

High-Throughput Digit-Level Systolic Multiplier Over GF(2<sup>m</sup>) Based on Irreducible Trinomials.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Low-Latency High-Throughput Systolic Multipliers Over GF(2<sup>m</sup>) for NIST Recommended Pentanomials.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2<sup>m</sup>) Using Symmetric TMVP and Block Recombination Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2<sup>m</sup>) Using Generalized (a, b)-Way Karatsuba Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters.
Proceedings of the 28th International Conference on VLSI Design, 2015

Efficient subquadratic parallel multiplier based on modified SPB of GF(2<sup>m</sup>).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Critical-path optimization for efficient hardware realization of lifting and flipping DWTs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fine-grained pipelining for multiple constant multiplications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Efficient Integer DCT Architectures for HEVC.
IEEE Trans. Circuits Syst. Video Technol., 2014

Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation.
IET Image Process., 2014

Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A novel DA-based architecture for efficient computation of inner-product of variable vectors.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

High-speed multiplier block design based on bit-level critical path optimization.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Reconfigurable CORDIC architectures for multi-mode and multi-trajectory operations.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Low-Complexity Multiplier for GF(2<sup>m</sup>) Based on All-One Polynomials.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials.
IEEE Trans. Very Large Scale Integr. Syst., 2013

CORDIC Designs for Fixed Angle of Rotation.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm.
IEEE Trans. Signal Process., 2013

Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT.
IEEE Trans. Circuits Syst. Video Technol., 2013

Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic.
IEEE Trans. Computers, 2013

Special section on image and video processing for security.
Signal Image Video Process., 2013

Zero-quantised discrete cosine transform coefficients prediction technique for intra-frame video encoding.
IET Image Process., 2013

Guest Editorial: Advanced Techniques for Efficient Electronic System Design.
Circuits Syst. Signal Process., 2013

An Efficient Look-up Table-based Approach for Multiplication over GF(2<sup>m</sup>) Generated by Trinomials.
Circuits Syst. Signal Process., 2013

A fast 8×8 integer Tchebichef transform and comparison with integer cosine transform for image compression.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Flexible integer DCT architectures for HEVC.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A variable quantization technique for image compression using integer Tchebichef transform.
Proceedings of the 9th International Conference on Information, 2013

2012
Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression.
VLSI Design, 2012

High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

New encoded single-indicator sequences based on physico-chemical parameters for efficient exon identification.
Int. J. Bioinform. Res. Appl., 2012

Low-latency area-delay-efficient systolic multiplier over GF(2<sup>m</sup>) for a wider class of trinomials using parallel register sharing.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A low-complexity spectrum sensing technique for cognitive radios based on correlation of intra-segment decimated vectors.
Proceedings of the IEEE International Conference on Communication Systems, 2012

2011
Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames.
IEEE Trans. Signal Process., 2011

Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT.
IEEE Trans. Signal Process., 2011

Development of Laguerre Neural-Network-Based Intelligent Sensors for Wireless Sensor Networks.
IEEE Trans. Instrum. Meas., 2011

A Self-Configurable Systolic Architecture for Face Recognition System Based on Principal Component Neural Network.
IEEE Trans. Circuits Syst. Video Technol., 2011

The Role of Combined OSR and SDF Method for Pre-Processing of Microarray Data that Accounts for Effective Denoising and Quantification.
J. Signal Inf. Process., 2011

Improved Comb Filter based Approach for Effective Prediction of Protein Coding Regions in DNA Sequences.
J. Signal Inf. Process., 2011

Guest Editorial: Special Issue on Embedded Signal Processing Circuits and Systems for Cognitive Radio-Based Wireless Communication Devices.
Circuits Syst. Signal Process., 2011

High-Speed RS(255, 239) Decoder Based on LCC Decoding.
Circuits Syst. Signal Process., 2011

High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

MCM-based implementation of block FIR filters for high-speed and low-power applications.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A New Look-Up Table Approach for High-Speed Finite Field Multiplication.
Proceedings of the International Symposium on Electronic System Design, 2011

Efficient coefficient partitioning for decomposed DA-based inner-product computation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A high-speed FIR adaptive filter architecture using a modified delayed LMS algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula.
Proceedings of the Fifth International Conference on Genetic and Evolutionary Computing, 2011

2010
Efficient Systolic Designs for 1- and 2-Dimensional DFT of General Transform-Lengths for High-Speed Wireless Communication Applications.
J. Signal Process. Syst., 2010

Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2<sup>m</sup>) Using Multiple Parity Prediction Schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT.
IEEE Trans. Circuits Syst. Video Technol., 2010

LUT Optimization for Memory-Based Computation.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth.
Integr., 2010

Efficient bit-parallel multipliers over finite fields GF(2<sup>m</sup>).
Comput. Electr. Eng., 2010

Novel input coding technique for high-precision LUT-based multiplication for DSP applications.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

DNA microarray analysis using Equalized Orthogonal Mapping.
Proceedings of the International Joint Conference on Neural Networks, 2010

An improved SOM-based visualization technique for DNA microarray data analysis.
Proceedings of the International Joint Conference on Neural Networks, 2010

Area-efficient parallel-prefix Ling adders.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed-Solomon Codec.
IEEE Trans. Very Large Scale Integr. Syst., 2009

On Efficient Implementation of Accumulation in Finite Field Over GF(2<sup>m</sup>) and its Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Efficient FPGA Realization of CORDIC With Application to Robotic Exploration.
IEEE Trans. Ind. Electron., 2009

Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

50 Years of CORDIC: Algorithms, Architectures, and Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Nonlinear channel equalization for wireless communication systems using Legendre neural networks.
Signal Process., 2009

Scalable Serial-parallel Multiplier over GF(2<sup>m</sup>) by Hierarchical Pre-reduction and Input Decomposition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

New Approach to LUT Implementation and Accumulation for Memory-based Multiplication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Computationally efficient FLANN-based intelligent stock price prediction system.
Proceedings of the International Joint Conference on Neural Networks, 2009

An optimized design for serial-parallel finite field multiplication over <i>GF</i>(2<sup><i>m</i></sup>) based on all-one polynomials.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic.
IEEE Trans. Signal Process., 2008

Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms.
IEEE Trans. Circuits Syst. Video Technol., 2008

Neural-Network-Based Robust Linearization and Compensation Technique for Sensors Under Nonlinear Environmental Influences.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Systolic and Super-Systolic Multipliers for Finite Field GF(2<sup>m</sup>) Based on Irreducible Trinomials.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

New Approach to Scalable Parallel and Pipelined Realization of Repetitive Multiple Accumulations.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

WMicaD: A New Digital Watermarking Technique Using Independent Component Analysis.
EURASIP J. Adv. Signal Process., 2008

Content-based image retrieval using orthogonal moments heuristically.
Proceedings of the IEEE International Conference on Systems, 2008

Development of intelligent sensors using Legendre functional-link artificial neural networks.
Proceedings of the IEEE International Conference on Systems, 2008

Support vector machine application in drug discovery of aldose reductase inhibitors.
Proceedings of the IEEE International Conference on Systems, 2008

Robust CRT-based watermarking technique for authentication of image and document.
Proceedings of the IEEE International Conference on Systems, 2008

Legendre-FLANN-based nonlinear channel equalization in wireless communication system.
Proceedings of the IEEE International Conference on Systems, 2008

Determination of QSAR of aldose reductase inhibitors using an RBF network.
Proceedings of the IEEE International Conference on Systems, 2008

Discrete tchebichef transform-A fast 4x4 algorithm and its application in image/video compression.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transforms.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Efficient Bit-Parallel Multipliers in Composite Fields.
Proceedings of the 3rd IEEE Asia-Pacific Services Computing Conference, 2008

2007
New Systolic Algorithm and Array Architecture for Prime-Length Discrete Sine Transform.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

DNA Microarray Data Analysis: Effective Feature Selection for Accurate Cancer Classification.
Proceedings of the International Joint Conference on Neural Networks, 2007

Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2<sup>m</sup>).
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Systolic Designs for DCT Using a Low-Complexity Concurrent Convolutional Formulation.
IEEE Trans. Circuits Syst. Video Technol., 2006

Scalable and modular memory-based systolic architectures for discrete Hartley transform.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Efficient Systolic Implementation of DFT Using a Low-Complexity Convolution-Like Formulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Highly concurrent reduced-complexity 2-D systolic array for discrete Fourier transform.
IEEE Signal Process. Lett., 2006

A novel neural network-based linearization and auto-compensation technique for sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low-complexity technique for secure storage and sharing of biomedical images.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A new approach to secure distributed storage, sharing and dissemination of digital image.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Financial Prediction of Major Indices using Computational Efficient Artificial Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2006

A New SOM-based Visualization Technique for DNA Microarray Data.
Proceedings of the International Joint Conference on Neural Networks, 2006

Field Programmable Gate Array Implementation of a Neural Network-based Intelligent Sensor System.
Proceedings of the Ninth International Conference on Control, 2006

Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Improved SVD-Based Watermarking Technique for Image and Document Authentication.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Reduced-Complexity Concurrent Systolic Implementation of the Discrete Sine Transform.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A 2-D Systolic Array for High-Throughput Computation of 2-D Discrete Fourier Transform.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Design of a fully-pipelined systolic array for flexible transposition-free VLSI of 2-D DFT.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Area-Time Efficient Systolic Architecture for the DCT.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
WAP-teletext system.
IEEE Trans. Consumer Electron., 2004

2003
Low-Power Transform-Domain Coding by Separable Two-Dimensional Hartley-Like Transform.
Proceedings of the International Conference on Embedded Systems and Applications, 2003

2002
Prospects of Group-Based Communication in Mobile Ad hoc Networks.
Proceedings of the Distributed Computing, 2002

Reconfigurable execution core for high performance DSP applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Effective communication in ad hoc network of mobile users group.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002


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