Lilian Bossuet
Orcid: 0000-0001-7964-3137Affiliations:
- University of Lyon, Saint-Etienne, France
According to our database1,
Lilian Bossuet
authored at least 113 papers
between 2003 and 2024.
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Bibliography
2024
IACR Cryptol. ePrint Arch., 2024
2023
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
IACR Cryptol. ePrint Arch., 2023
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023
Combined Internal Attacks on SoC-FPGAs: Breaking AES with Remote Power Analysis and Frequency-based Covert Channels.
Proceedings of the IEEE European Symposium on Security and Privacy, 2023
Proceedings of the IEEE European Symposium on Security and Privacy, 2023
Proceedings of the Smart Card Research and Advanced Applications, 2023
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023
2022
IACR Cryptol. ePrint Arch., 2022
IACR Cryptol. ePrint Arch., 2022
Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Proceedings of the Smart Card Research and Advanced Applications, 2022
2021
Efficiency through Diversity in Ensemble Models applied to Side-Channel Attacks - A Case Study on Public-Key Algorithms -.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021
Improving Deep Learning Networks for Profiled Side-channel Analysis Using Performance Improvement Techniques.
ACM J. Emerg. Technol. Comput. Syst., 2021
The use of ellipse-based estimator as a sub-key distinguisher for Side-Channel Analysis.
Comput. Electr. Eng., 2021
Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Security Assessment of Heterogeneous SoC-FPGA: On the Practicality of Cache Timing Attacks.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level.
Proceedings of the IEEE European Symposium on Security and Privacy Workshops, 2021
Proceedings of the Advances in Cryptology - EUROCRYPT 2021, 2021
Multi-Spot Laser Fault Injection Setup: New Possibilities for Fault Injection Attacks.
Proceedings of the Smart Card Research and Advanced Applications, 2021
2020
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020
IEEE Trans. Computers, 2020
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the European Conference on Circuit Theory and Design, 2020
Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
Backtracking Search for Optimal Parameters of a PLL-based True Random Number Generator.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Online Performance Evaluation of Deep Learning Networks for Profiled Side-Channel Analysis.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020
2019
Experimental Study of Locking Phenomena on Oscillating Rings Implemented in Logic Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Secure Internal Communication of a Trustzone-Enabled Heterogeneous Soc Lightweight Encryption.
Proceedings of the International Conference on Field-Programmable Technology, 2019
2018
Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
IEEE Trans. Inf. Forensics Secur., 2017
Microprocess. Microsystems, 2017
Area-oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti-counterfeiting schemes.
Int. J. Circuit Theory Appl., 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the International Conference on Field Programmable Technology, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
2016
Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators.
IEEE Trans. Inf. Forensics Secur., 2016
Comments on "A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-per-Device Licensing".
IEEE Trans. Inf. Forensics Secur., 2016
IEEE Trans. Computers, 2016
Microprocess. Microsystems, 2016
Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE).
Microprocess. Microsystems, 2016
Fault model of electromagnetic attacks targeting ring oscillator-based true random number generators.
J. Cryptogr. Eng., 2016
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
Proceedings of the 8th IFIP International Conference on New Technologies, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Proceedings of the 11th European Workshop on Microelectronics Education, 2016
2015
Microprocess. Microsystems, 2015
An Ultra-Lightweight Transmitter for Contactless Rapid Identification of Embedded IP in FPGA.
IEEE Embed. Syst. Lett., 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015
Identification of embedded control units by state encoding and power consumption analysis.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015
Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design Protection.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
2014
A PUF Based on a Transient Effect Ring Oscillator and Insensitive to Locking Phenomenon.
IEEE Trans. Emerg. Top. Comput., 2014
Sustain. Comput. Informatics Syst., 2014
Survey of hardware protection of design data for integrated circuits and intellectual properties.
IET Comput. Digit. Tech., 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
2013
Architectures of flexible symmetric key crypto engines - a survey: From hardware coprocessor to multi-crypto-processor system on chip.
ACM Comput. Surv., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the HASP 2013, 2013
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
2012
Secure Extension of FPGA General Purpose Processors for Symmetric Key Cryptography with Partial Reconfiguration Capabilities.
ACM Trans. Reconfigurable Technol. Syst., 2012
Des. Autom. Embed. Syst., 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Contactless Electromagnetic Active Attack on Ring Oscillator Based True Random Number Generator.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012
2011
Fast Digital Post-Processing Technique for Integral Nonlinearity Correction of Analog-to-Digital Converters: Validation on a 12-Bit Folding-and-Interpolating Analog-to-Digital Converter.
IEEE Trans. Instrum. Meas., 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Cryptographic Extension for Soft General-Purpose Processors with Secure Key Management.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Area optimization of ROM-based controllers dedicated to digital signal processing applications.
Proceedings of the 18th European Signal Processing Conference, 2010
2008
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2008
A new orthogonal online digital calibration for time-interleaved analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Orthogonal correction implementation for time interleaved analog-to-digital converters: Realtime application.
Proceedings of the 2008 16th European Signal Processing Conference, 2008
2007
EURASIP J. Embed. Syst., 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Tech. Sci. Informatiques, 2006
Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Int. J. Embed. Syst., 2006
An offset and gain calibration method for time-interleaved analog to digital converters.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 11th European Test Symposium, 2006
2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Communication Costs Driven Design Space Exploration for Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Fast Design Space Exploration Method for Reconfigurable Architectures.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003