Mahesh Vaidya
Orcid: 0000-0001-9422-415X
According to our database1,
Mahesh Vaidya
authored at least 7 papers
between 1987 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
Proposal to Achieve the Ultimate Holding Voltage Tunability in Silicon Controlled Rectifiers (SCRs) for a Wide Range of ESD Protection Application.
Proceedings of the IEEE International Reliability Physics Symposium, 2025
Novel Trigger Circuit & SCR Device Co-Engineering Based Local (I/O-VSS & I/O-VDD) ESD Clamp Concepts with Improved Latch-Up Susceptibility, Lower Leakage and Lower Capacitance for Ultra High Speed I/Os.
Proceedings of the IEEE International Reliability Physics Symposium, 2025
2024
Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Proceedings of the IEEE International Reliability Physics Symposium, 2024
2022
Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
1987