Maheshwar Chandrasekar

According to our database1, Maheshwar Chandrasekar authored at least 10 papers between 2008 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
A novel diagnostic test generation methodology and its application in production failure isolation.
Proceedings of the 2016 IEEE International Test Conference, 2016

2011
Fault Collapsing Using a Novel Extensibility Relation.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A Novel Learning Framework for State Space Exploration Based on Search State Extensibility Relation.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2010
Search State Extensibility based Learning Framework for Model Checking and Test Generation.
PhD thesis, 2010

Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation.
J. Electronic Testing, 2010

DFT + DFD: An Integrated Method for Design for Testability and Diagnosability.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Fast circuit topology based method to configure the scan chains in Illinois Scan architecture.
Proceedings of the 2009 IEEE International Test Conference, 2009

Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

C preprocessor use in numerical tools: an empirical analysis.
Proceedings of the 47th Annual Southeast Regional Conference, 2009

2008
Guided test generation for isolation and detection of embedded trojans in ics.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008


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