Makio Uchida

According to our database, Makio Uchida authored at least 3 papers between 1995 and 2000.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2000

Switching well noise modeling and minimization strategy for digitalcircuits with a controllable threshold voltage scheme.

Akio Koyama, Makio Uchida, Tatsuhiro Aida, Jun'ya Kudo, Masatoshi Tsuge

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999

Switching well noise analysis and minimization strategy for low V_th CMOS integrated circuits.

Akio Koyama, Masatoshi Tsuge, Jun'ya Kudo, Tatsuhiro Aida, Makio Uchida

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1995

A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits.

Toshiro Takahashi, Makio Uchida, Takahiko Takahashi, Ryozo Yoshino, Masakazu Yamamoto, Nobuh Kitamura

IEEE J. Solid State Circuits, December, 1995