Masatoshi Tsuge

According to our database, Masatoshi Tsuge authored at least 4 papers between 1999 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS.

Takayasu Norimatsu, Takashi Kawamoto, Kenji Kogo, Naohiro Kohmu, Fumio Yuki, Norio Nakajima, Takashi Muto, Junya Nasu, Takemasa Komori, Hideki Koba, Tatsunori Usugi, Tomofumi Hokari, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Masatoshi Tsuge, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS.

Takashi Kawamoto, Takayasu Norimatsu, Kenji Kogo, Fumio Yuki, Norio Nakajima, Masatoshi Tsuge, Tatsunori Usugi, Tomofumi Hokari, Hideki Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Jun Kumazawa, Hiroaki Kurahashi, Takashi Muto, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2000

Switching well noise modeling and minimization strategy for digitalcircuits with a controllable threshold voltage scheme.

Akio Koyama, Makio Uchida, Tatsuhiro Aida, Jun'ya Kudo, Masatoshi Tsuge

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999

Switching well noise analysis and minimization strategy for low V_th CMOS integrated circuits.

Akio Koyama, Masatoshi Tsuge, Jun'ya Kudo, Tatsuhiro Aida, Makio Uchida

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999