Manfred Schlägl

According to our database, Manfred Schlägl authored at least 10 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV.

Manfred Schlägl, Jonas Reichhardt, Daniel Große

Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

Late Breaking Results: Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators.

Katharina Ruep, Manfred Schlägl, Daniel Große

Proceedings of the Design, Automation & Test in Europe Conference, 2026

A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture.

Manfred Schlägl, Andreas Hinterdorfer, Daniel Große

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

Control Flow Protection by Cryptographic Instruction Chaining.

Shahzad Ahmad, Stefan Rass, Maksim Goman, Manfred Schlägl, Daniel Große

Proceedings of the 22nd International Conference on Security and Cryptography, 2025

ProtoLens: Dynamic Transaction Visualization in Virtual Prototypes.

Manfred Schlägl, Jonas Reichhardt, Daniel Große

Proceedings of the Forum on Specification & Design Languages, 2025

Fast Interpreter-Based Instruction Set Simulation for Virtual Prototypes.

Manfred Schlägl, Daniel Große

Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024

Single Instruction Isolation for RISC-V Vector Test Failures.

Manfred Schlägl, Daniel Große

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level.

Manfred Schlägl, Moritz Stockinger, Daniel Große

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development.

Manfred Schlägl, Daniel Große

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V.

Lucas Klemmer, Manfred Schlägl, Daniel Große

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022