Lucas Klemmer

Orcid: 0000-0002-2571-1058

According to our database1, Lucas Klemmer authored at least 10 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV.
CoRR, 2023

Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis.
Proceedings of the Forum on Specification & Design Languages, 2023

2022
An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Formal Verification of SUBLEQ Microcode implementing the RV32I ISA.
Proceedings of the Forum on Specification & Design Languages, 2022

Waveform-based performance analysis of RISC-V processors: late breaking results.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

EPEX: Processor Verification by Equivalent Program Execution.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020


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