Daniel Große
Orcid: 0000-0002-1490-6175Affiliations:
- JKU Linz, Austria
- University of Bremen, Germany (former)
According to our database1,
Daniel Große
authored at least 181 papers
between 2001 and 2023.
Collaborative distances:
Collaborative distances:
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Online presence:
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on jku.at
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on twitter.com
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on orcid.org
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on id.loc.gov
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on dl.acm.org
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Bibliography
2023
Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV.
CoRR, 2023
GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the Forum on Specification & Design Languages, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization.
Proceedings of the 22nd Formal Methods in Computer-Aided Design, 2022
Proceedings of the Forum on Specification & Design Languages, 2022
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform.
J. Syst. Archit., 2021
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata.
Microprocess. Microsystems, 2020
RISC-V based virtual prototype: An extensible and configurable platform for the system-level.
J. Syst. Archit., 2020
Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling.
Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation: Applications, 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the Integrated Formal Methods - 16th International Conference, 2020
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Early Verification of ISA Extension Specifications using Deep Reinforcement Learning.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the Forum for Specification and Design Languages, 2020
Towards Generation of a Programmable Power Management Unit at the Electronic System Level.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes<sup>*</sup>.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side<sup>*</sup>.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the Automated Technology for Verification and Analysis, 2020
2019
Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction.
Int. J. Softw. Tools Technol. Transf., 2019
Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is <i>NP</i>-complete (Research Note).
ACM J. Emerg. Technol. Comput. Syst., 2019
it Inf. Technol., 2019
fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits.
CoRR, 2019
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 Forum for Specification and Design Languages, 2019
Proceedings of the 2019 Forum for Specification and Design Languages, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019
2018
IPSJ Trans. Syst. LSI Des. Methodol., 2018
Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters<sup>*</sup>.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018
Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 Forum on Specification & Design Languages, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Approximate hardware generation using symbolic computer algebra employing grobner basis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Int. J. Softw. Tools Technol. Transf., 2017
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017
Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
An adaptive prioritized <i>ε</i>-preferred evolutionary algorithm for approximate BDD optimization.
Proceedings of the Genetic and Evolutionary Computation Conference, 2017
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2017
Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach.
Proceedings of the 2017 Forum on Specification and Design Languages, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016
Guided lightweight Software test qualification for IP integration using Virtual Prototypes.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the Genetic and Evolutionary Computation Conference, 2016
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016
On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
Formal verification of integer multipliers by combining Gröbner basis with logic reduction.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Towards formal verification of real-world SystemC TLM peripheral models - a case study.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Quantitative timing analysis of UML activity diagrams using statistical model checking.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Precise error determination of approximated components in sequential circuits with model checking.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the Computer Aided Verification - 28th International Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules.
Proceedings of the Automated Technology for Verification and Analysis, 2015
2014
Funktionale Abdeckungsanalyse von C-Programmen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis.
Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2013
Proceedings of the 8th International Workshop on Automation of Software Test, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Verifying SystemC using an intermediate verification language and symbolic simulation.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
J. Multiple Valued Log. Soft Comput., 2012
CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012
Proceedings of the International Symposium on Electronic System Design, 2012
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
Proceedings of the Graph Transformations - 6th International Conference, 2012
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Designing a RISC CPU in Reversible Logic.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2011
Proceedings of the First International Workshop on Design and Implementation of Formal Tools and Systems, 2011
Proceedings of the 2011 Forum on Specification & Design Languages, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
IEEE Embed. Syst. Lett., 2010
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
J. Multiple Valued Log. Soft Comput., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the Forum on specification and Design Languages, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008
Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Qualitätsorientierter Entwurfs- und Verifikationsablauf für digitale Systeme [Quality-Driven Design and Verification Flow for Digital Systems].
Proceedings of the Ausgezeichnete Informatikdissertationen 2008, 2008
Proceedings of the Languages for Embedded Systems and their Applications, 2008
Proceedings of the Forum on specification and Design Languages, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Formal Verification on the Word Level using SAT-like Proof Techniques.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the Forum on specification and Design Languages, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005
Proceedings of the Correct Hardware Design and Verification Methods, 2005
2004
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004
2003
it Inf. Technol., 2003
Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Proceedings of the Forum on specification and Design Languages, 2003
2002
Genet. Program. Evolvable Mach., 2002
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002
2001
Proceedings of the Computational Intelligence, 2001