Manoj Kumar

Orcid: 0000-0002-1863-4189

Affiliations:
  • Guru Gobind Singh Indraprastha University, New Delhi, India
  • Guru Jambheshwar University of Science & Technology, Hisar, India (former)


According to our database1, Manoj Kumar authored at least 17 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Online presence:

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Bibliography

2023
A PVT tolerant low power wide tuning range differential voltage controlled oscillator design in 90 nm CMOS technology.
Integr., November, 2023

2021
A Common-Gate Current-Reuse UWB LNA for Wireless Applications in 90 nm CMOS.
Wirel. Pers. Commun., 2021

Low power CMOS differential ring VCO designs using dual delay stages in 0.13 ​μm technology for wireless applications.
Microelectron. J., 2021

Low Power XNOR based Single Ended VCO Circuit Design with Dynamic Threshold MOS.
Proceedings of the IC3 2021: Thirteenth International Conference on Contemporary Computing, Noida, India, August 5, 2021

2020
Low power active load and IMOS varactor based VCO designs using differential delay stages in 0.18 ​μm technology.
Microelectron. J., 2020

2019
A 3-14 GHz, Self-Body Biased Common-Gate UWB LNA for Wireless Applications in 90 nm CMOS.
J. Circuits Syst. Comput., 2019

Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz-6.1 GHz Applications in 0.18 μm CMOS.
J. Circuits Syst. Comput., 2019

2018
Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs.
Microprocess. Microsystems, 2018

A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control.
J. Circuits Syst. Comput., 2018

Design of Linear Low-Power Voltage-Controlled Oscillator with I-MOS Varactor and Back-Gate Tuning.
Circuits Syst. Signal Process., 2018

2016
Design of low power two bit magnitude comparator using adiabatic logic.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016

Modified 4-2 compressor using improved multiplexer for low power applications.
Proceedings of the 2016 International Conference on Advances in Computing, 2016

2012
Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate
CoRR, 2012

Design of 9-transistor single bit full adder.
Proceedings of the Second International Conference on Computational Science, 2012

2011
Voltage Controlled Ring Oscillator Design with Novel 3 Transistors XNOR/XOR Gates.
Circuits Syst., 2011

Design of CMOS Energy Efficient Single Bit Full Adders.
Proceedings of the High Performance Architecture and Grid Computing, 2011

2010
Level Shifter Design for Low Power Applications
CoRR, 2010


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