Marco Annaratone

According to our database1, Marco Annaratone authored at least 16 papers between 1983 and 1998.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

1998
Warp Architecture and Implementation.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1994
Digital Equipment Corporation High Performance Fortran on Workstation Farms.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

1992
A Set of New Mapping and Coloring Heuristics for Distributed-Memory Parallel Processors.
SIAM J. Scientific Computing, 1992

1991
The K2 distributed memory parallel processor: architecture, compiler, and operating system.
Proceedings of the Proceedings Supercomputing '91, 1991

Architecture, Implementation and System Software of K2.
Proceedings of the Distributed Memory Computing, 2nd Euronean Conference, 1991

1990
The K2 Parallel Processor: Architecture and Hardware Implementation.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

Parallelization of FORTRAN code on distributed-memory parallel processors.
Proceedings of the 4th international conference on Supercomputing, 1990

1989
K9: a simulator of distributed-memory parallel processors.
Proceedings of the Proceedings Supercomputing '89, Reno, NV, USA, November 12-17, 1989, 1989

Performance Measurements on a Commercial Multiprocessor Running Parallel Code.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

Interprocessor Communication Speed and Performance in Distributed-memory Parallel Processors.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

1987
The Warp Computer: Architecture, Implementation, and Performance.
IEEE Trans. Computers, 1987

Applications and Algorithm Partitioning on Warp.
Proceedings of the COMPCON'87, 1987


1986
Warp Architecture and Implementation.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

1985
SPLASH: A framework for chip design and layout.
Integration, 1985

1983
A multiplier with multiple error correction capability.
Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983


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