Robert S. Cohn

According to our database1, Robert S. Cohn authored at least 32 papers between 1987 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2016
Simulation and Analysis Engine for Scale-Out Workloads.
Proceedings of the 2016 International Conference on Supercomputing, 2016

2014
Characterizing EVOI-Sufficient k-Response Query Sets in Decision Problems.
Proceedings of the Seventeenth International Conference on Artificial Intelligence and Statistics, 2014

2011
Portable trace compression through instruction interpretation.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Comparing Action-Query Strategies in Semi-Autonomous Agents.
Proceedings of the Twenty-Fifth AAAI Conference on Artificial Intelligence, 2011

2010
Analyzing Parallel Programs with Pin.
Computer, 2010

Dynamic program analysis of Microsoft Windows applications.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

Selecting Operator Queries Using Expected Myopic Gain.
Proceedings of the 2010 IEEE/WIC/ACM International Conference on Intelligent Agent Technology, 2010

2009
Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware.
IEEE Trans. Computers, 2009

Scalable support for multithreaded applications on dynamic binary instrumentation systems.
Proceedings of the 8th International Symposium on Memory Management, 2009

2008
08441 Final Report - Emerging Uses and Paradigms for Dynamic Binary Translation.
Proceedings of the Emerging Uses and Paradigms for Dynamic Binary Translation, 26.10., 2008

2007
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

2006
Automatic logging of operating system effects to guide application-level architecture simulation.
Proceedings of the Joint International Conference on Measurement and Modeling of Computer Systems, 2006

A Cross-Architectural Interface for Code Cache Manipulation.
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

2005
Persistence in dynamic code transformation systems.
SIGARCH Comput. Archit. News, 2005

Controlling program execution through binary instrumentation.
SIGARCH Comput. Archit. News, 2005

Introduction to the special issue.
SIGARCH Comput. Archit. News, 2005

Pin: building customized program analysis tools with dynamic instrumentation.
Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

2004
PIN: a binary instrumentation tool for computer architecture research and education.
Proceedings of the 2004 workshop on Computer architecture education, 2004

Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

2002
Profile-guided post-link stride prefetching.
Proceedings of the 16th international conference on Supercomputing, 2002

2001
Code layout optimizations for transaction processing workloads.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

2000
Design and Analysis of Profile-Based Optimization in Compaq's Compilation Tools for Alpha.
J. Instr. Level Parallelism, 2000

1998
Optimizing Alpha Executables on Windows NT with Spike.
Digit. Tech. J., 1998

1996
Hot Cold Optimization of Large Windows/NT Applications.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1991
Source Level Debugging of Automatically Parallelized Code.
Proceedings of the ACM/ONR Workshop on Parallel and Distributed Debugging, 1991

1990
Supporting Systolic and Memory Communciation in iWarp.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

1989
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor.
Proceedings of the ASPLOS-III Proceedings, 1989

1988
Warp: an integrated solution of high-speed parallel computing.
Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988

1987
Programming Warp.
Proceedings of the COMPCON'87, 1987



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