Maria Isabel Mera

Orcid: 0000-0001-7067-8667

Affiliations:
  • Escuela Superior Politécnica del Litoral (ESPOL), Guayaquil, Ecuador


According to our database1, Maria Isabel Mera authored at least 7 papers between 2014 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
It's a Big Tiny(ML) World in Industry 4.0 and 5.0.
Proceedings of the 9th International Conference on Algorithms, Computing and Systems, 2025

ARIES: Autonomous Reconnaissance, Inspection and Exploration System for Hybrid Single and Multi-UAV Building Inspection Approach after Disaster.
Proceedings of the Companion of the 2025 ACM International Joint Conference on Pervasive and Ubiquitous Computing, 2025

2020
Do Not Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication.
IEEE Embed. Syst. Lett., 2020

SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

2017
Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression.
ACM Trans. Embed. Comput. Syst., 2017

2016
Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2014
Trade-offs in execution signature compression for reliable processor systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


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