Brett H. Meyer

According to our database1, Brett H. Meyer authored at least 55 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors.
Des. Autom. Embed. Syst., 2020

Surprisal-Triggered Conditional Computation with Neural Networks.
CoRR, 2020

Using Speech Synthesis to Train End-To-End Spoken Language Understanding Models.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Partitioning and Selection of Data Consistency Mechanisms for Multicore Real-Time Systems.
ACM Trans. Embed. Comput. Syst., 2019

Efficient CMOS Invertible Logic Using Stochastic Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Characterizing the Effectiveness of Hot Sparing on Cost and Performance-per-Watt in Application Specific SIMT.
Integr., 2019

ARINC-825TBv2: A Hardware-in-the-Ioop Simulation Platform for Aerospace Security Research.
Proceedings of the 30th International Workshop on Rapid System Prototyping, 2019

Learning Recurrent Binary/Ternary Weights.
Proceedings of the 7th International Conference on Learning Representations, 2019

2018
Efficient Performance Evaluation of Multi-Core SIMT Processors with Hot Redundancy.
IEEE Trans. Emerg. Top. Comput., 2018

Mapping and Scheduling Mixed-Criticality Systems with On-Demand Redundancy.
IEEE Trans. Computers, 2018

Study of Stochastic Invertible Multiplier Designs.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression.
ACM Trans. Embed. Comput. Syst., 2017

Multi-armed bandits for efficient lifetime estimation in MPSoC design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Stochastic Computing Can Improve Upon Digital Spiking Neural Networks.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Sparse-Clustered Network with Selective Decoding for Internet Traffic Classification.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Neural networks designing neural networks: multi-objective hyper-parameter optimization.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Bounding error detection latency in safety critical systems with enhanced Execution Fingerprinting.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

A four-mode model for efficient fault-tolerant mixed-criticality systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Techniques for on-demand structural redundancy for massively parallel processor arrays.
J. Syst. Archit., 2015

Task placement and selection of data consistency mechanisms for real-time multicore applications.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Yield-aware Performance-Cost Characterization for Multi-Core SIMT.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

RotR: Rotational redundant task mapping for fail-operational MPSoCs.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Hot spare components for performance-cost improvement in multi-core SIMT.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Cost-effective lifetime and yield optimization for NoC-based MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2014

Architecture implications of pads as a scarce resource.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Linear regression techniques for efficient analysis of transistor variability.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

MB-FICA: multi-bit fault injection and coverage analysis.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Trade-offs in execution signature compression for reliable processor systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Walking pads: Fast power-supply pad-placement optimization.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core.
IEEE Micro, 2013

Architectural implications of spatial thermal filtering.
Integr., 2013

2012
ArchFP: Rapid prototyping of pre-RTL floorplans.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

2011
Thermal benefit of multi-core floorplanning: A limits study.
Sustain. Comput. Informatics Syst., 2011

Reducing the cost of redundant execution in safety-critical systems using relaxed dedication.
Proceedings of the Design, Automation and Test in Europe, 2011

Cost-effective safety and fault localization using distributed temporal redundancy.
Proceedings of the 14th International Conference on Compilers, 2011

2010
Slack allocation for yield improvement in NoC-based MPSoCs.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Temperature-to-power mapping.
Proceedings of the 28th International Conference on Computer Design, 2010

Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs.
Proceedings of the Design, Automation and Test in Europe, 2010

A case for lifetime-aware task mapping in embedded chip multiprocessors.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC.
Des. Autom. Embed. Syst., 2009

2007
Amdahl's Law Revisited for Single Chip Systems.
Int. J. Parallel Program., 2007

Rethinking Automated Synthesis of MPSoC Architectures.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2005
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors.
IEEE Trans. Computers, 2005


  Loading...