Marius Evers

According to our database, Marius Evers authored at least 10 papers between 1996 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.

Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari

Proceedings of the 2007 International Symposium on Physical Design, 2007

2001

Understanding branches and designing branch predictors for high-performance microprocessors.

Marius Evers, Tse-Yu Yeh

Proc. IEEE, 2001

2000

Improving branch prediction by understanding branch behavior.

Marius Evers

PhD thesis, 2000

1998

Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures.

Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt

Int. J. Parallel Program., 1998

Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing.

Sanjay J. Patel, Marius Evers, Yale N. Patt

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work.

Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

Variable Length Path Branch Prediction.

Jared Stark, Marius Evers, Yale N. Patt

Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1997

Improving branch prediction accuracy by reducing pattern history table interference.

Po-Yung Chang, Marius Evers, Yale N. Patt

Int. J. Parallel Program., 1997

One Billion Transistors, One Uniprocessor, One Chip.

Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark

Computer, 1997

1996

Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches.

Marius Evers, Po-Yung Chang, Yale N. Patt

Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996